Motorola Corporation

Robert S Kaltenecker

Robert E Stengel

James S Irwin

Ralph T Enderby

Andrzej T Guzik

Bill Tabano Agar, Jr

Joseph A Budano, Ii

Frederick C Wernett

Alvin D Kluesing

Daniel C Brayton

Jeffrey K Jones

Henry L Pfitzenmayer

An active bias compensation circuit (110) senses a quiescent current flowing in an amplifier (130) and adjusts the quiescent current to maintain an optimal DC biasing of the amplifier (130) over a wide range of factors, e.g., temperature variation, process variation, history of the amplifier (130), etc. The compensation circuit (110) includes two transistors (101, 102) forming a difference amplifier. A sensing voltage proportional to the quiescent current and a reference voltage are applied to the base electrodes of the two transistors (101, 102), which generates a bias signal in response to a difference between the sensing voltage and the reference voltage. The bias signal adjusts the quiescent current in the amplifier (130).

Amplifier with active bias compensation and method for adjusting

An amplifier circuit (30) has the capability for driving a large number of loads while still maintaining the desirable gain response. The amplifier circuit (30) includes two push-pull amplifier circuits (31 and 41). A first push-pull amplifier circuit (31) has a pair of bipolar transistors (33 and 34) connected in a cascode circuit configuration and a second pair of bipolar transistors (35 and 36) connected in a cascode circuit configuration. In addition, the second push-pull amplifier circuit (41) has a first pair of bipolar transistors (43 and 44) connected in a cascode circuit configuration and a second pair of bipolar transistors (45 and 46) connected in a cascode circuit configuration. The channel distortion and gain response of the amplifier circuit (30) are significantly improved by the push-pull amplifier circuits (31 and 41).

Dual push-pull amplifier circuit and method

A method for designing and making an RF transformer has been provided. The method utilizes a model for an RF transformer wherein the model has parameters that directly relate to a physical construction of the components of the transformer, namely, a core and a twisted wire. The method separates the core from the twisted wire so that characteristics of each can be separately determined. These determined characteristics are then optimized and used to design and make a transformer.

Method for designing a transformer

A circuit for compensating a cascode amplifier has been provided. The circuit includes a capacitor and an inductor for enhancing the stability of the amplifier and for extending the usable frequency range of the amplifier by maintaining the group delay of the amplifier substantially constant over a large frequency range. With such a compensated amplifier, an improved CTB distortion performance in the upper operating frequency range of the amplifier is achieved with increased stability. In other words, the bandwidth of the amplifier is extended with improved stability and distortion performance.

Circuit for compensating an amplifier

A resistor having a novel physical geometry is provided. The physical geometry of the resistor minimizes the current paths through the resistor such that the reactance components of the resistor is minimized for radio frequency operation. The resistor is made from a resistive material such as chrome silicon oxide, nichrome. The physical geometry of the resistor layout reduces the physical area occupied by the resistor, and also results in lower sensitivity to a DC trimming procedure used in the manufacturing process.

Resistor having geometry for enhancing radio frequency performance

A novel circuit and method for providing amplitude and phase compensation for a balun in order to provide first and second voltage signals that are balanced has been provided. The compensation is achieved by adding an amplitude and phase compensation circuit such as a transmission line (14) or inductive (20) and capacitive (22) lumped elements in series with one of the ports of the balun on the balanced side. The amplitude and phase compensation circuit includes a characteristic impedance parameter (Zo) and an electrical length parameter (Eo) that are optimized such that the amplitude difference between first and second voltage signals is minimized, while the magnitude of the phase difference between first and second voltage signals is maximized.

Circuit and method for balun compensation

A rigid, monolithic structure for the resonator elements of a tuned stripline segment which may be adjusted by simple, low cost techniques. The resonator elements use a stripline segment (23,24) made from conductive layers of a multilayer printed circuit board. This structure allows the stripline segment to be totally enclosed in a solid, incompressible dielectric material (15,17) which is essentially immune to microphonic effects. A plurality of shorting holes (21) are fabricated at one end of the stripline which serve to short circuit the stripline segment (23) to the ground conductors (18,19) on the layers above and below the stripline segment (23). Adjustment of the resonant frequency is accomplished by removing the plated conductor inside one of the holes at a time, thus removing the short, until the desired resonant frequency is obtained.

Resonant circuit element having insignificant microphonic effects

A transmission line transformer is used for impedance matching in high frequency, broadband applications. The characteristic impedance, Z.sub.o, of the transmission line transformer is adjusted to an optimum value by terminating the ends of the transmission line using variable capacitors. The capability to trim the transmission line transformer to an optimum value of Z.sub.o reduces the criticality of the various factors which influence Z.sub.o during the manufacturing process.

Variable Z.sub.o transmission line transformer

A dual FET oscillator includes a first J-FET and a second J-FET connected to it as a source follower. A turned circuit is connected to the gate of the first J-FET and to the second J-FET. Bias voltage is supplied to both J-FET's. Schottky diodes are connected to both J-FET's to limit gate-source voltage.

Dual FET oscillator

A Ga As FET oscillator includes an FET having gate-drain and source connections. A tuned circuit is connected to the FET gate. Bias voltage is supplied to the FET. A parallel-connected resistor and capacitor is connected to the FET source. A Schottky diode is connected across the FET gate-source junction and the parallel connected resistor and capacitor, with its anode connected to the FET gate and its cathode connected to the resistor and capacitor. The Schottky diode limits the positive voltage across the gate-source junction of the Ga As FET to prevent gate-source current flow.

FET oscillator circuit

The molded resonator includes at least one formed resonator element having an resonator portion and opposed end leg portions which provide electrical connections to the main portion. A dielectric portion is molded about the resonator element. A conductive ground plane is carried by the dielectric portion and electrically shields the resonator element. The resonator element is formed of wire having a circular cross-section.

Growing community of inventors

Mesa, AZ, United States of America

Robert S Kaltenecker