Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Robert S Jones, Iii

Xiankun Jin

Tao Chen

Juxiang Ren

Peijun Wang

Douglas Alan Garrity

Jules D Campbell, Jr

Mike Robert Garrard

Christian R Ahrens

Jeffrey D Ganger

Colin McAndrew

Jiang Chen

Brett J Thompsen

Alex A Ford

Scott Willard Herrin

Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Compensated alternating polarity capacitive structures

A temperature sensor circuit that includes two banks of bipolar transistors where the bipolar transistors of each bank are coupled in parallel in a current leg of the sensor circuit. The current legs are configured to produce voltages and currents that are dependent upon the temperature sensitivity of the bipolar transistors in the current legs. The sensor circuit includes a controller that, in some embodiments, periodically enables subsets of the bipolar transistors of each of bank during operation.

Temperature sensor circuit

A circuit for high accuracy element matching is provided. The circuit includes an analog to digital converter (ADC) configured to generate an output code. A current source is configured to provide a signal to the ADC. The current source includes a first current branch including a first unit element group having a first unit element coupled by way of a first set of switches to a first node and a second node and a second unit element coupled by way of a second set of switches to the first node and the second node. A second current branch includes a second unit element group having a third unit element coupled by way of a third set of switches to the first node and the second node and a fourth unit element coupled by way of a fourth set of switches to the first node and the second node. A control circuit is configured to provide control signals to the sets of switches based on the output code. The control circuit is further configured to sort unit element currents and to dynamically switch unit elements.

High accuracy matching system and method therefor

An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array.

Optimized arrays for segmented successive-approximation-register (SAR) analog-to-digital converter (ADC)

A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit. A first terminal of the second variable resistor circuit is coupled to a first test port and a second terminal of the second variable resistor circuit is coupled to a second test port to allow for a resistance measurement of the second variable resistor circuit during a test mode. The current source circuit includes a non-volatile storage circuit configured to store a tap value generated during the test mode corresponding to a set of select signal values for the second plurality of tap inputs which provides a desired resistance of the second variable resistor circuit as determined during the test mode and to provide a set of select signal values for the first plurality of tap inputs based on the tap value stored in the non-volatile storage circuit.

Current source with variable resistor circuit

The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.

Multiplying digital to analog converter (MDAC) with error compensation and method of operation

A redundant signed digit (RSD) analog to digital converter (ADC) includes an amplifier, a first variable capacitance circuit coupled to a first input to the amplifier, a second variable capacitance circuit coupled to a second input to the amplifier, a third variable capacitance circuit coupled to a first output of the amplifier, and a fourth variable capacitance circuit coupled to a second output of the amplifier. An output of the third and fourth capacitance circuits are coupled to one another and to inputs to the first and second variable capacitance circuits. Capacitance values of the first, second, third and fourth variable capacitance circuits are higher when inputs to the ADC correspond to a selected number of more significant bits than when inputs to the ADC correspond to a remaining number of less significant bits.

Redundant signed digit (RSD) analog to digital converter

A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.

Sigma-delta modulator with trimmed reference voltage for quantizer

A redundant signed digit (RSD) analog to digital converter (ADC) receives a high voltage (VRH) and a low voltage (VRL) for use in converting an input signal to a digital signal. A doubling circuit receives the input signal and doubles the input signal to provide a doubled input signal using an amplifier and a first capacitor. The first capacitor has a capacitance of a first magnitude. A VR circuit continues processing the doubled input signal to provide a 2VR signal. A Vref circuit (VR+Cand C) provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal. The first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage. The second capacitor has a capacitance equal to half that of the first capacitor.

Low power cycle data converter

An analog to digital converter has an input circuit, a computation circuit, an initialization circuit, and an output circuit. The input circuit is for receiving an analog signal and has a pair of outputs. A computation circuit has a pair of inputs coupled to the pair of outputs. The computation circuit has an amplifier having a pair of complementary outputs (Outp, Outn). The initialization circuit is coupled to the complementary outputs and is for biasing the complementary outputs at a time prior to the computation circuit beginning a computation on the analog signal. The output circuit is coupled to the pair of complementary outputs and provides a digital signal.

Analog to digital converter with amplifier

An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.

Analog-to-digital converter with variable gain and method thereof

A RSD analog to digital converter has an RSD stage that in turn has a switched capacitor integrator (SCI). The SCI uses an operational amplifier. A capacitor, which operates as a offset compensation capacitor, is precharged to the offset voltage of the operational amplifier during a precharge phase. The next phase switches this offset compensation capacitor in the path of the capacitors which are used to perform the integration. The effect is that the offset of the operational amplifier is corrected by the use of the compensation capacitor that had been precharged to the offset voltage during the previous phase.

RSD analog to digital converter

A method for operating a circuit in an analog to digital converter, including providing a resistor network ( ) having a plurality of resistor banks ( ) connected together, each resistor bank of the plurality of resistor banks having a plurality of resistors ( ) connected together in series and a plurality of first switches ( ) for selecting a node ( ) between adjacent resistors, and a plurality of second switches ( ) for selecting a chosen resistor bank of the plurality of resistor banks. A first switch is closed in a chosen resistor bank to charge a parasitic capacitance ( ), and a second switch is closed after closing the first switch, and after charging the parasitic capacitance in the chosen resistor bank.

Apparatus for converting an analog signal utilizing resistor D/A converter precharging

A data processing system (,) includes a plurality of modules (,) and an analog-to-digital converter (ADC) (,). The ADC (,) includes at least one port terminal (,) for transmitting test information from the ADC (,). The plurality of modules (,) and the ADC (,) are coupled to a central processing unit (CPU) (,) via an intermodule bus (,). A tester can exchange test information with the ADC (,) directly through the port terminal (,) instead of using the intermodule bus (,). Also, various sub-modules (,) of the ADC (,) can be independently tested without performing a conversion process.

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Austin, TX, United States of America

Robert S Jones, Iii