International Business Machines Corporation

Robert S Jaffe

John Samuel Batchelder

Byron Edward Dom

Raymond E Bonner

Mark Alan Lavin

Hungwen Li

Rick A Rand

William G Pope

Jon R Mandeville

Ming-Cheng Sheng

Denos Constantinos Gazis

Margaret M Kienzle

Paul Schreiner

A system for providing a centrally planned, completely general routing system that assigns traffic routes to maintain optimal traffic system stability. The system includes a plurality of fixed computers, linked by a wide area network, which can communicate seemlessly with all vehicles in a region via a wireless communication system. The system is interactive, in that the fixed computers receive data such as desired route, position and segment transit time data from individual in-vehicle computer units and determine and communicate the system optimal route to each such in-vehicle unit.

Optimal and stable route planning system

A two-dimensional input/output system for a massively parallel SIMD computer system providing an interface for the two-way transfer of data between a host computer and the SIMD computer. A plurality of buffers equal in number, and distributed with the individual processing elements of the SIMD computer are used to provide a temporary storage area which allows data in different formats to be mapped in a format suitable for transfer to the host computer or for transfer to the SIMD processing elements. The temporary storage is controlled in such a way as to transfer entire blocks of data in a single SIMD system clock cycle thereby achieving an input/output data rate of N bits/cycle for a SIMD computer consisting of N processors. The system is capable of handling irregular as well as regular data structures. The system also emphasizes a distributed approach in having the input/output system divided into N pieces and distributed to each processor to reduce the wiring complexity while maintaining the I/O rate.

Input/output system for a massively parallel, single instruction,

A system is described which determines the characteristics of a substantially rounded feature, such as via hole in a printed circuit board. The system includes an image scanner for providing a serial flow of a raster scan image of pixels which represent the rounded feature. Tangent detecting circuits are further provided which select groups (i.e., neighborhoods) of pixels from the scan image, each group including pixels clustered about a plurality of chosen azimuths and adjacent to a tangent to a boundary of the rounded feature. Processing circuits are further provided to trim each selected group of pixels to eliminate pixels not lying on the tangent line. The pixels which remain after the trim operation are representative of the limits (e.g., diameter, radius, etc.) of the rounded feature and enable an analyzing circuit to determine the characteristics of the rounded feature by examining the relationships between the tangent line pixels. A second system is described which reduces the apparatus required for trimming the selected pixel groups. A tangent segment is fed into a plurality of parallel networks which initially identify right and left shoulders of the tangent segment. The identified shoulders are expanded and used as a mask on the original tangent segment to disconnect a central plateau thereof from its next lower and non-central plateaus. Subsequent trimming enables the central plateau to be identified.

System for detecting and analyzing rounded objects

A method and apparatus for automatic inspection of periodic patterns typically found on patterned silicon wafers, printed circuit board, and the like is disclosed herein. The method comprises an inspection algorithm of two parts: a low-level algorithm and a higher level algorithm. The low-level algorithm utilizes the known periodically of the pattern to find defects by comparing identical cells in the periodic array. The high-level algorithm applies the low-level algorithm, some number of times (N) in succession on the image; accumulates defective pixels to form a separate image; and then applies a threshold-sort operation on a neighborhood to determine center pixel defectiveness. The apparatus for implementing the above method comprises a parallel/pipeline architecture for high speed processing and RAM LUT's to implement a plurality of subtract and compare functions.

System for automatic inspection of periodic patterns

A scanning imager is described which includes a line camera and a table to mechanically present successive regions of an item to be imaged. The time of exposure of the camera for each successive region presented is controlled by encoding strips connected to the table. Thus, if the table is subjected to motion variations, the encoding strips are likewise affected and vary the exposure time for each analog image pixel scan. To compensate, an exposure correction system is provided which includes an analog voltage generator whose output is related to each successive region exposure time. An A to D conversion circuit is responsive to the analog voltage to normalize the analog image value from the camera so that, in effect, equal exposure images result.

Exposure compensation for a line scan camera

A method and apparatus for automatic inspection of periodic patterns typically found on patterned silicon wafers, printed circuit board, and the like is disclosed herein. The method comprises an inspection algorithm of two parts: a low-level algorithm and a higher level algorithm which includes, therein the operation of the low-level algorithm. The low-level algorithm utilizes the known periodicity of the pattern to find defects by comparing identical cells in the periodic array. The high-level algorithm comprises applying the low-level algorithm, some number of times (N) in succession on the image. An accumulator image is formed by adding the results of the low-level algorithm to create a separate image array where the pixels relate to the number of times that the pixel in the original image was detected as defective by the low-level algorithm. The apparatus for implementing the above method comprises a parallel/pipeline architecture for high speed processing and RAM LUT's to implement a plurality of subtract and compare functions.

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Shenorock, NY, United States of America

Robert S Jaffe