Digital Equipment Corporation

Other

Fujitsu Corporation

Robert S Grondalski

Atul Dhablania

Takumi Maruyama

James Vinh

Pranjal Srivastava

Ajay Naini

Systems and methods are described for conscious digital data processing systems. These may include storing data in a set of associated nodes and performing relational operations on this data. In certain instances, the execution of instructions is recorded and new sequences of instructions are synthesized. These recorded instructions may be later spontaneously selected for execution. Values associated with the data may be kept in an array and the behavior of the digital data processing system tailored according to those values.

Method and system for the architecture and implementation of a conscious machine

A computer-implemented method and system for performing an arithmetic shift right by n of an m-bit negative number. A right shifter executes a logical shift right operation on the number to be shifted. A left shifter performs a left shift on an m-bit mask of ones, left shifting the mask by the one's complement of n. An OR operation is then performed on the results of the two shifting operations, producing the desired arithmetic shift right result.

Generation of sign extended shifted numerical values

A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

Method and apparatus for reduction of noise sensitivity in dynamic logic circuits

A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements for carrying data messages between the processing elements, wherein each of the processing elements of the plurality of processing elements includes a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element over the interconnection network to another processing element among the plurality of processing elements; and a parity checking circuit for checking parity of a second data message as it is received by that processing element over the the interconnection network, the parity checking and parity generating circuits being separate from each other and enabling that processing element to generate parity for the first data message being sent by that processing element while simultaneously checking parity of the second message received by that processing element.

Simultaneous parity generating/reading circuit for massively parallel

An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The system further includes a shift register which can shift data either toward a shift-in terminal, or toward a shift-out terminal, either one bit at a time or four bits at a time, thus improving processing system speed for floating point arithmetic operations.

Shift register divided into a number of cells and a number of stages

An array processing system including a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing elements including an input multiplexer having a multiplexer output line and a plurality of multiplexer input lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; an output demultiplexer having a demultiplexer input line and a plurality of demultiplexer output lines each of which is connected to a different member of the group of nearest neighbor processing elements for that processing element; and a control circuit, which responds to a broadcast control signal by electrically coupling the input multiplexer output line in that processing element to the output demultiplexer input line in that processing element.

Mechanism for broadcasting data in a massively parallell array

An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communications paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path. Thus, the stage may attempt to transfer a message over another path associated with the same address.

Massively parallel array processing system

Massively parallel array processing system with processors selectively

An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communucations paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path. Thus, the stage may attempt to transfer a message over another associated with the same address.

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Maynard, MA, United States of America

Robert S Grondalski