Mostek Corporation

Robert S Green

Harold Wallace Dozier

Robert J Proebsting

Vernon G McKenny

Vernon D McKenny

An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs. By repeated masking and implanting steps, selected MOSFETs are implanted with differing doses of ions and combinations of doses, thereby forming circuit portions with MOSFETs having threshold voltages tailored to optimize different characteristics associated with different circuit portions.

Method of making a plurality of MOSFETs having different threshold

Threshold voltage regulation of field-effect transistors on a common substrate of an integrated circuit is achieved by adjusting the back bias on the substrate using a charge pump that is selectively operated whenever the threshold voltage of a designated enhancement mode FET falls below a reference voltage. A voltage divider provides the reference voltage that is applied to the gate of the enhancement mode FET, which when turned-on enables the charge pump.

Integrated circuit with threshold regulation

The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.

High performance inverter circuits

A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multiplexed into row address latches and column address latches through six address pins by sequentially occurring row address and column address strobes. Sixty-four bits of information from an address row are read and transferred to a sixty-four bit column register. One bit of the column register is then selected by the column address decoder so that data is transferred from that bit to a data output latch. Data is transferred into a data input latch and then to the addressed bit of the storage matrix as well as to the addressed column register by a write signal. Upon completion of the row address strobe cycle, each cell in the address row is automatically refreshed by the data in the respective bit of the column register, including the bit which may have been modified by a write cycle. The state of the data output latch remains valid until a subsequent column address strobe is received. The write signal to the chip provides for a read only or a write only cycle, in addition to the read-modify-write cycle. In the absence of a chip select, the data output assumes an open circuit condition. The sense amp utilizes a dynamic differential amplifier to sense a voltage change of a precharged column bus. The entire system is substantially entirely dynamic in operation and accordingly has very low power consumption.

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Richardson, TX, United States of America

Robert S Green