Ncr Corporation

E-systems, Inc.

Robert S Gordy

David E Sanders

Ramon P Chambers

Cameron E Morrison

Billy R Poston

Alfred T Anderson

William H Mosley, Jr

Lex A Scott

Frequency indication pulses are applied to comparison and feedback logic for the identification of a frequency in a selected frequency band. The comparison and feedback logic is part of an identification circuit that includes a main memory for storing representations of frequency values that is coupled to the comparison and feedback logic by data transfer gating. Control logic coupled to the data transfer gating and main memory provides shift pulses, clock pulses and control signals to sequence the operation of the main memory and comparison and feedback logic. Interval timing and control logic receives from the RF section of the compressive receiver a compare signal, a manual set signal and clock pulses to generate inhibit and enable signals for the comparison and feedback logic, and the control logic. When a comparison in the comparison and feedback logic between a received frequency indication pulse and a memory bit from the main memory indicates the presence of a new frequency, frequency value information, in the form of a sixteen bit data word, is transferred to interface logic and interface memory that encodes a digital word representing a specific frequency occurring within the time constrained subinterval. This digital word representation of a specific frequency is applied to an interface bus as frequency data available to the other sections of the compressive receiver.

Frequency identification circuit

A radio receiver is disclosed in which a received signal is amplified, filtered, and then sampled at a rate determined by a clock signal produced by a selectable-rate, digital oscillator. In sampling the received signal, a family of harmonics are generated which are distributed in a pattern determined by the sampling rate. One harmonic is selected as an intermediate frequency signal and, like the received signal, it is amplified, filtered, and sampled. The second sampling process is driven by a second clock signal produced by a variable-rate, digital oscillator. This produces a second family of harmonics which are derived from the intermediate frequency signal. The second clock signal rate is selected to produce one harmonic which has a carrier component centered on zero frequency. This harmonic, which is the desired baseband signal, is separated from the other harmonics by means of a low-pass filter. The baseband signal is amplified and provided to the user, while at the same time, it is passed through a narrow bandwidth, low-pass filter to extract the carrier component of the signal. The extracted carrier component is digitized to generate a signal that controls the frequency of the variable-rate, digital oscillator. This creates a phase locked loop wherein the variable-rate, digital oscillator generates a clock signal at a rate that maintains the carrier component of the baseband signal centered on zero frequency.

Phase locked sampling radio receiver

An anti-jam PN sequence spread spectrum conferencing communication system is disclosed for simultaneously transmitting and receiving in a plurality of communications channels secure voice communications. All received messages are modulated with the same pseudo noise sequence and arrive at any given channel at random time states, wherein the messages are separated, separately processed and finally conferenced, using a technique based upon the correlation of the PN sequence and dependent upon the randomness of the epoch state of a given PN sequence coded with a message in relation to the other coded messages.

Spread spectrum conferencing communication system

Improved acquisition of signals in a Gaussian noise environment is achieved by applying the output of a correlator (14) to a threshold detector (12). A correlation pulse output from the threshold detector (12) and the output of the correlator (14) are input to a false alarm processor (10) that includes multiple correlation checking channels (22). Each correlation checking channel (22) is assigned to sample an input at various points over a selected interval by an enable pulse generated at the output of select logic (30). Each correlation checking channel (22) includes correlation check enable logic (34), a blanking generator (36), and a confirmation logic (42). In the confirmation logic (42) samples of the analog input are taken at discrete times and integrated over a preselected number of intervals. If this integrated value exceeds a threshold level during the integration interval, the analog input signal is considered valid and a 'signal confirmed' pulse is generated and gated through a gate NAND (44) onto a signal confirm line 28.

False alarm processor

A biphase shift keyed modulated carrier is input to an analog delay line having a plurality of sampling taps time spaced along the line. The modulated input carrier is sampled at a rate four times the carrier frequency to produce amplitude samples of the input. The taps of the delay line are divided into two groups comprising alternate tap sets and the amplitude samples of each group are summed for decoding the I and Q channels of a modulated carrier. The summed signal of each of the channels is input to an individual sample and hold circuit which aliases the carrier frequency to baseband. The output of the first sample and hold circuit of each channel is provided to a second sample and hold circuit for the respective channels. The second sample and hold circuit of each channel is clocked at a data rate derived from a bit timing loop. An estimation of the data is produced by each of the second sample and hold circuits with the data produced by the second sample and hold circuit of one channel providing a recovered carrier signal output. Further, the data produced by each of the second sample and hold circuits, after inversion in one line by means of an inverting amplifier, is input to a phase comparator. The output of the phase comparator is filtered and used to drive a voltage controlled oscillator that generates the clock pulses to operate the first sample and hold circuits and also to clock the delay line.

Phase/frequency controlled phase shift keyed signal carrier

Acquisition of a carrier frequency lock and a symbol timing lock is efficiently achieved during the preamble of a data signal in a time division multiple access communication system by first operating the system in an acquisition mode and subsequently switching to a data recovery mode. In the acquisition mode, an input signal is passed through a transversal correlator and frequency multiplied by a factor of two. The multiplied signal is used to control a local oscillator for demodulating the carrier signal. Also in the acquisition mode, the output of the transversal correlator is envelope detected and applied to a symbol timing loop that produces a symbol timing signal. Upon the detection of a symbol timing lock, a lock detector switches the system to the data recovery mode. In the data recovery mode, the input signal is frequency multiplied by 4 and used to control the local oscillator for demodulating the input signal. The demodulated input signal is now applied to the symbol timing loop to maintain a symbol timing lock condition.

Apparatus for the acquisition of a carrier frequency and symbol timing

A radio receiver is disclosed which measures the statistics of an interfering narrow band noise signal and from these statistics generates a function which when mixed at baseband with a data signal combined with the narrow band noise reduces the interfering effect of the noise signal. The interference eliminating function is generated by processing signals representing an approximation of the data, the covariance of the narrow band noise interference, the noise figure for the receiver and the amplitude of the data signal. As the function is generated it is input to a mixer together with the combined narrow band noise and data signal. Iterated processing improves the estimation for the noise statistics thereby improving the approximation for the resulting data signal. This further enhances the solution for the noise elimination function thereby still further improving the desired data signal, thus creating a positive improving feedback loop.

Adaptive narrow band noise estimator/suppressor radio receiver

The carrier suppression circuit of the present invention is utilized to minimize electrical imbalances within double-balanced mixers. The circuit operates upon a modulating signal, having at least two states so as to adjust the dwell time that the signal stays in a particular state to counteract the effects of electrical imbalance within the mixer. Minimization of the electrical imbalance provides a greater suppression of the carrier signal which, in turn, improves the quality of the signal both at the transmitter and at the receiver.

Compensation circuit for an electrical signal mixer

A four phase to two phase correlator is incorporated within the demodulator section of a spread spectrum modem to process a received RF signal modulated by a transmitted PN code and a digital data signal. The correlator includes a first modulator for combining the channel 1 and channel 2 R code signals with the received RF input signal to generate a first channel 1 RF signal and a first channel 2 RF signal. The first channel 1 RF signal is modulated by the transmitted PN code signal, the channel 1 R code signal and the digital data signal. The first channel 2 RF signal is modulated by the transmitted PN code signal, the channel 2 R code signal and the digital data signal. A second modulator combines the channel 1 and channel 2 PN code signals and the channel 1 and channel 2 R code signals with a first unmodulated RF signal to generate a second channel 1 RF signal which is modulated by the channel 1 PN code signal and by the channel 1 R code signal, and a second channel 2 RF signal which is modulated by the channel 2 PN code signal by the channel 2 R code signal. A third modulator combines both channels of the first and second RF signals to generate a third RF signal which is modulated only by the digital data signal.

Four phase to two phase correlator

A correlator error detector generates a first repeating digital pseudo noise code signal which is compared in a correlator to a second signal generated by the error detector with the second signal having the same pseudo noise code but with a noise signal intentionally added. The error detector measures the capability of the correlator to correlate the first signal with the second signal under varying noise conditions. Errors produced by the correlator are counted, and classified as being either missed correlation outputs or false correlation outputs.

Transversal correlator error detector

The detector of the present invention includes a first and a second signal channel each of which is adapted to receive a spread spectrum signal, or any other similar type multi-modulated carrier signal. In the preferred embodiment of the invention, the first signal channel is provided with a correlator for partially demodulating the received signal, as to one modulation signal component, with a demodulation signal derived from the second signal channel. The first signal channel is also provided with an additional correlator for demodulating the partially demodulated signal as to another modulation component. The second signal channel is comprised of a means for generating a dithered demodulation signal which signal is driven into synchronization with a corresponding modulation signal component in the received signal so as to enable the accurate generation of the demodulation signal utilized by the first signal channel.

Spread spectrum detector

An offset error correction circuit for improved reception of signals by compensating for any offset error voltage produced by a phase detector in the absence of an input signal to the detector. The error correction circuit translates the offset error voltage into a digital value and stores that value in a counter. When a PSK signal is applied to the circuit, the error correction circuit subtracts the stored value of the offset error voltage from the output of the phase detector which compensates for the offset error. The compensation for the offset error provides an improved signal to noise ratio.

Offset correction circuit for phase detectors

Apparatus for indicating a phase lock condition between an incoming multiphase carrier signal and a local oscillator in a phase-locked loop demodulator. A phase error signal is generated by phase comparing the carrier signal and the local oscillator signal. The phase error signal is rectified and the result detected for a range of values that indicate a phase lock condition. Phase lock exists when the phase error signal is within selected voltage ranges. After detection, the error signal is low-pass filtered and compared to a predetermined threshold value to generate a phase-lock indication signal. In the last two steps, an indication signal is generated to signify that the phase error signal is in the range of voltage values corresponding to phase lock for a greater percentage of time than it is within this range with the loop is not phase locked.

Carrier lock detector

Apparatus and method are provided to discriminate between true locking of a phase-locked loop on the main lobe of an information signal, and false locking on a side lobe thereof. The energy in the locked signal is sensed and compared with the signal energy at fixed frequency increments, preferably twice the bit clock rate frequency, above and below the lock frequency. A greater energy content at the increment frequencies than at the locked frequency indicates a false lock condition and is used to inhibit the loop from entering a locked mode.

Apparatus and method for inhibiting false locking of a phase-locked loop

A digitized automatic gain controlled amplifier and gain hysteresis circuit is disclosed for preserving a low frequency, low level modulation at the output of an AGC amplifier while also providing for rapid correction of amplifier gain for large variations in the amplifier input signal level. The described amplifier is particularly adapted to satellite communications systems in which ionospheric changes produce rapid power fades and wherein satellite tracking is accomplished by dithering a high-gain antenna on the satellite to produce a low-frequency power amplitude control signal at the input to the AGC amplifier, which control signal is allowed to pass through to a control system while the larger input signal variations are gain-controlled out.

Growing community of inventors

Largo, FL, United States of America

Robert S Gordy