Intel Corporation

Robert S Dreyer

Shekhar Yeshwant Borkar

Hans J Mulder

Donald B Alpert

Frederick J Pollack

Daniel G Lau

Tsu-Hua Wang

William M Corwin

Calvin E Wells

Naomi Obinata

Mohammad A Abdallah

Larry M Mennemeier

Michael J Keith

Srinivas Chennupaty

Michael A Julier

Ticky Thakkar

Mike J Tripp

Nimish H Modi

Katherine Kong

An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.

System and method for performing an insert-extract instruction

An apparatus is provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided is an apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided is an apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided is an apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Method and apparatus for retrofit mounting a VLSI chip to a computer chassis for current supply

A method and apparatus are provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are a method and apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are a method and apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are a method and apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Apparatus for retrofit mounting a VLSI chip to a computer chassis for

A system which includes a chassis having a first side and a second side; a circuit board having a set of components, the first circuit board mounted on the first side of the chassis; an integrated circuit package mounted on the second side of the chassis; and a set of electrical connections providing a communications network between the circuit board and the integrated circuit package; wherein the integrated circuit package is thermally coupled to the second side of the chassis.

System for connecting subsystems of dissimilar thermal properties

Apparatus for mounting a chip package to a chassis of a computer

An apparatus is provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided are an apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided are an apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided are an apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Apparatus for mounting a very large scale integration (VLSI) chip to a

Method and apparatus for mounting a very large scale integration (VLSI)

A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Apparatus and method for identifying the features and the origin of a

An identification apparatus and method for identifying the microprocessor, including a read-only memory for storing microprocessor ID data having data fields for identifying the microprocessor, and control logic for executing an ID instruction that reads the microprocessor ID data from the read-only memory and stores it in a register that can be selectively read by a programmer. The identification apparatus and method also include an ID flag indicative of implementation of the ID instruction in the microprocessor, and a test flag program for testing the ID flag to determine whether or not to execute the ID instruction. The method is available at any time while the microprocessor is operating, for example during initialization of the system software, installation of a program, or while a program is running. Once a microprocessor has been identified, features appropriate to the specific microprocessor can be enabled, and work-around programs can be installed. The method prevents execution of the ID instruction on microprocessors that do not have the identification system, and prevents execution of the test flag program on microprocessors that do not have a test flag location. The invention is particularly useful for groups of compatible microprocessor families whose development is continually advancing with introduction of new families and models.

Apparatus and method using an ID instruction to identify a computer

Input signals in floating-point format are converted into output signals in integer format while handling saturation cases appropriately. Saturation exists when the value of an input signal is outside the output range. Saturation cases are detected by invoking an integer comparison instruction using signals in floating-point format as inputs to tile integer comparison instruction. When implemented in software on processors such as the Intel.RTM. Pentium.TM. processor, using an integer comparison instruction to compare signals in floating-point format provides more efficient signal conversion than conventional schemes that use a floating-point comparison instruction to compare floating-point signals.

Fast floating-point to integer conversion

Apparatus and method for identifying a computer microprocessor

An apparatus for measuring and monitoring various parameters that contribute to the performance of a processor includes a pair of programmable event counters for counting any two independent events selected from a predetermined list of processor events. A specialized register controls the operation of the event counters and also selects the events to be counted. The contents of the event counters can be accessed either by a supervisor mode program which reads an instruction or through a special access port.

Apparatus for monitoring the performance of a microprocessor

A microprocessor is disclosed herein with an idle mode of operation. The microprocessor provides a very quick interrupt that can be asserted externally. A Run/Stop (R/S) pin on the chip is asserted to access and hold the idle mode. The R/S pin is electrically connected to a central control unit. An additional pin, which may be termed an 'acknowledge pin', is provided to indicate when the microprocessor is in the idle state. The R/S pin and the acknowledge pin can be useful for any operation in which the microprocessor must be stopped quickly, and can be used for bus control, debugging, diagnostics, multi-processor synchronization, and direct memory access operations. The idle mode is asserted between instructions, at an instruction boundary following execution of one instruction, but before execution of the next, when the execution unit has completed all its modifications of registers, flags, and memory for a first instruction, but before it begins this modification for the next instruction following in the pipeline. In the idle mode, the decoder does not issue instructions into the pipeline, but the clock operates normally and other microprocessor functions are operable. A port may be provided, with a secondary control unit for issuing simple instructions directly to the execution unit, bypassing the normal instruction issue process. The present invention can be useful for implementing debugging and remote diagnostic systems, and also for synchronizing microprocessors running in parallel.

Microprocessor having a run/stop pin for accessing an idle mode

A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.

Growing community of inventors

Palo Alto, CA, United States of America

Robert S Dreyer