Intel Corporation

Other

Microsoft Technology Licensing, LLC

Robert S Chappell

Jason W Brandt

Joseph Nuzman

Barry E Huntley

Scott Dion Rodgers

Rajesh S Parthasarathy

Gilbert A Neiger

Lihu Rappoport

David W Burns

Elmoustapha Ould-Ahmed-Vall

Martin Guy Dixon

Ravi Rajwar

Ronak Singhal

Jared Warner Stark, Iv

Hermann Gartler

Madhavan Parthasarathy

David M Durham

Ravi L Sahita

Bret L Toll

Vedvyas Shanbhogue

Christopher J Hughes

Jesus Corbal

Edward Thomas Grochowski

Stephen H Gunther

Matthew C Merten

David B Papworth

Manohar Ruben Castelino

Thomas R Huff

James D Allen

Vijaykumar Balaram Kadgi

Ho-Seop Kim

Buford M Guy

Mayank Bomb

Glenn J Hinton

Raanan Sade

Raj K Ramanujan

Konrad K Lai

Stanislav Shwartsman

Srikanth T Srinivasan

Shlomo Raikin

Asit K Mallick

Sergiu D Ghetie

Deepak K Gupta

Alexandre J Farcy

Rodrigo Branco

Rohit Bhatia

Stephen J Robinson

Scott P Bobholz

Chunhui Zhang

James Hadley

Ilhyun Kim

Ryan Carlson

Zhongying Zhang

Gur Hildesheim

Wojciech S Powiertowski

Sagar V Dalvi

Prasoonkumar Surti

Vinodh Gopal

Gilbert M Wolrich

Subramaniam M Maiyuran

Zeev Sperber

Mohan J Kumar

Wajdi K Feghali

James D Guilford

Varghese George

Rajesh M Sankaran

Hong Wang

Kirk S Yap

Alexander F Heinecke

Richard A Uhlig

Ravishankar Iyer

Sreenivas Subramoney

Avinash Sodani

Yen-Cheng Liu

Sanjay Kumar

Erdinc Ozturk

Sean M Gulley

Dan Baum

David Zimmerman

Kai Cheng

Igor Yanover

Sean Mirkes

Jorge E Parra

Li Zhao

Sailesh Kottapalli

Adi Yoaz

Jayesh Gaur

Ronen Zohar

Michael J Espig

Adrian C Moga

Hisham Shafi

Muthukumar Swaminathan

Zhen Fang

Subramanya R Dulloor

Wayne Alan Downer

Laura A Knauth

Daniel Sebastian Berger

Larry O Smith

Omar M Shaikh

Liron Zur

Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.

Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit

An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

Memory management apparatus and method for managing different page tables for different privilege levels

Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

Method and apparatus for approximation using polynomials

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

Microarchitectural mechanisms for the prevention of side-channel attacks

In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.

System, apparatus and method for a hybrid reservation station for a processor

A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.

System and method for replacement in associative memories using weighted PLRU trees

Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Virtualization exceptions

A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

Criticality based port scheduling

Growing community of inventors

Portland, OR, United States of America

Robert S Chappell