Nec America, Inc.

Interactive Systems, Inc.

Robert S Broughton

Brian F Reilly

William C Laumeister

David Delgadillo

Jeremy Smith

An adaptive clock duty cycle controller which generates a dc error signal that is supplied to a logic device, such as a logic inverter or a logic buffer, which outputs a specified duty cycle clock signal. The output of the logic device is supplied to a positive peak detector, a negative peak detector and an average signal level detector. The output of the positive peak detector and the negative peak detector are supplied to a mid-peak generating circuit which generates a signal for setting and maintaining the desired duty cycle. The signal output by the average signal level detector represents the average value of the output of the logic device. The signal output by the mid-peak generating circuit is compared with the signal output by the average signal level detector by an operational amplifier. The output of the operational amplifier represents the error signal which is supplied back to the input of the logic device to control the output of the logic device to the desired duty cycle.

Adaptive clock duty cycle controller

A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling either a direct digital synthesis circuit that provides a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. To minimize jitter and buffer spills (i.e., data overruns or underruns), the frequency and phase of the desynchronized clock is constantly varied to match the variations of the data rate of incoming SONET data. The DDS circuit generates the desynchronized clock, which has a center frequency equal to a predetermined frequency of a reference clock, whose phase is advanced or retarded in accordance with the magnitude of a tuning word supplied by a controller, which implements either a linear, non-linear, or fuzzy logic control algorithm. The controller periodically updates the tuning word in response to status variables to adjust the frequency of the clock output of the DDS circuit. In an alternative embodiment, a digital voltage controlled oscillator is used in place of the DDS circuit.

SONET DS-N desynchronizer

Method and apparatus for in-band, video broadcasting of commands to interactive devices are described. Control data are encoded by subliminally modulating, prior to the remote, composite video broadcast of video program material, a selected sequence of video image fields. The resulting modulated video fields within the viewing area of a television, each having alternately, proportionately raised and lowered luminance horizontal scan lines, are monitored by a light sensitive device positioned adjacent the user's television screen. A semirigid, twisted pair cable connects the device to nearby receiver/transmitter electronics that discriminate the binary data from the program material and amplitude modulate a high frequency infrared (IR) carrier with the data. Interactive devices, e.g. educational aids or action toys, within range of the wireless IR transmission detect energy in this frequency range, decode the commands embedded in the control data, and selectively execute predetermined actions in response to the data-encoded broadcast. In a proposed modification, low radio frequency (RF) electromagnetic radiation emanating from the television's raster scan electronics is coupled by a conventional RF antenna to the receiver electronics, which identically discriminate the binary data, from the program material, for transmission to the interactive devices.

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Beaverton, OR, United States of America

Robert S Broughton