Nxp B.v.

St-ericsson Sa

Nxp Usa, Inc.

Robert Rutten

Lucien Johannes Breems

Muhammed Bolatkale

Shagun Bajoria

Johannes Hubertus Antonius Brekelmans

Hendrik Van Der Ploeg

Manfred Zupke

Jan Van Sinderen

Martin Kessel

Evert-Jan Pol

Bernard Burdiek

Tjeu Van Ansem

Jan Niehof

Andries Pieter Hekstra

Massimo Ciacci

Robert Henrikus Margaretha Van Veldhoven

Johan Frederik Witte

Frits Anthonie Steenhof

Peter Van De Haar

Niels Gabriel

Mohammed Abo Alainein

Soheil Bahrami

Joerg Heinrich Walter Wenzel

Juergen Richard Marschner

Francoise Jeannette Harmsze

Albertus Willibrordus Oude Essink

Peter Blinzer

Lucien J M Breems

Robert Henrikus Van Veldhoven

A circuitis described comprising (i) a first digital-to-analog converter, (ii) a second digital-to-analog converter, (iii) a plurality of unit elements, and (iv) switching circuitry. The switching circuitryis adapted so that in a first switching state, a set of unit elementsof the plurality of unit elementsforms part of the first digital-to-analog converter, and in a second switching state, the set of unit elementsforms part of the second digital-to-analog converter. Furthermore, a corresponding method of operating a circuitis described.

Circuit with two digital-to-analog converters and method of operating such the circuit

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

Shuffler-free ADC error compensation

A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

System and method of calibration of sigma-delta converter using tone injection

A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

System and method of calibration of sigma-delta converter using injected signal correlation

An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

Offset compensation in ADC circuitry

Certain aspects of the disclosure are directed to in-phase/quadrature (IQ) mismatch detection and correction in radio frequency receivers. According to a specific example, a method of manufacture or use comprises, in a quadrature radio-frequency receiver configured to process signals using I and Q components, providing parameters indicative of IQ mismatches associated with circuitry of the quadrature radio-frequency receiver due to changes in signal gain. The method further includes, while using the quadrature radio-frequency receiver to receive and process a received radio signal, correcting for the IQ mismatches by using the parameters in response to actual signal gain change.

Quadrature radio receiver with gain-dependent mismatch correction

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Signal processing and conversion

The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.

IQ mismatch correction module

A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.

Data processor

Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.

Multiple-tap compensation and calibration

An RF reception system and method uses IF quadrature mixing, in which there is further mixing and channel filtering in the digital domain, to isolate a frequency of interest. A coefficient estimator is used for generating a phase correction coefficient and an amplitude correction coefficient from filtered in-phase and quadrature desired signals and from filtered in-phase and quadrature image signals.

Coefficient estimation for digital IQ calibration

Circuits and methods for jitter compensation in a receiver system are useful to improve performance. One such circuit includes a combiner block for combining a reference signal with an input signal (Sin) of the circuit, and a converter stage for converting the input signal (Sin) together with the reference signal. The converter stage is clocked by a clock signal modulated by a jitter signal. A forward path having a first mixer unit is provided for multiplying a copy of an output signal (A) of the converter stage with the frequency of the reference signal in order to generate a jitter compensating signal (B). A compensation unit for compensating jitter in the output signal (A) of the converter stage in a direct output path with the jitter compensating signal (B) is also provided.

Jitter compensation

A sigma-delta modulator ()) for converting an input signal (X(s)) (X(s)) to a quantized output signal (Y(z)) (Y(z)), in which a feedback loop is provided between a filter () and a quantizer () of the modulator, the feedback loop configured to reduce quantization errors from the modulator by filtering and subtracting quantization noise fed back to an input of the quantizer ().

Sigma-delta modulator

A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.

Method to linearize the output from an ADC

An analog to digital conversion circuit comprises a first digital noise cancellation filter () configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter () is has an input coupled to an input of the first digital noise cancellation filter (). Mutually different sets of at least one-filter coefficients are programmed in the first and second digital noise canceling filters (). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters () using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.

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Nistelrode, Netherlands

Robert Rutten