International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Robert Russell Robison

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Brent A Anderson

Christopher J Penny

Reinaldo Ariel Vega

Kisik Choi

Jed Hickory Rankin

William R Tonti

Rajasekhar Venigalla

Robert J Gauthier, Jr

Edward J Nowak

Michael A Guillorn

Toshiharu Furukawa

Gauri V Karve

Terence B Hook

Kiran V Chatty

Somnath Ghosh

Hari V Mallela

Tenko Yamashita

Ruqiang Bao

Fee Li Lie

Wagdi William Abadeer

Joseph M Lukaitis

Lyndon Ronald Logan

Marc Adam Bergendahl

John Ryan Sporre

Eric R Miller

Sean Teehan

Timothy Mathew Philip

Andres Bryant

Souvick Mitra

Tom C Lee

Christopher Stephen Putnam

Viorel C Ontalus

Michel J Abou-Khalil

Hasan Munir Nayfeh

Kangguo Cheng

Jeffrey P Gambino

Veeraraghavan S Basker

John J Ellis-Monaghan

Dechao Guo

Ping-Chuan Wang

Kirk David Peterson

Timothy Dooling Sullivan

Arvind Kumar

Jeffrey Bowman Johnson

Andrew Mark Greene

Koichi Motoyama

Jin Cai

Emre Alptekin

Ardasheir Rahman

Ruilong Xie

Chengwen Pei

Hosadurga K Shobha

Richard Quimby Williams

William F Clark, Jr

Huimei Zhou

Nivo Rovedo

Gen Tsutsui

Daniel James Dechene

Junjun Li

Juntao Li

Junli Wang

Nicolas J Loubet

Hemanth Jagannathan

Xin Ru Wang

Shreesh Narasimha

JunJun Li

Koji Watanabe

Anthony I Chou

Yun Shi

Huai Huang

Derrick Liu

Devendra K Sadana

Steven J Holmes

Tak H Ning

Oleg Gluschenkov

Charles W Koburger, Iii

Heng Wu

Sanjay C Mehta

Kai D Feng

Huiming Bu

Xuefeng Liu

Richard Anthony Conti

Kevin W Brew

Michael P Belyansky

Jay William Strane

Dan Moy

David L Harmon

Ephrem G Gebreselasie

Kimball M Watson

Youngseok Kim

Balasubramanian S Pranatharthi Haran

Hung H Tran

Adra Carr

Richard Andre Wachnik

Sungjae Lee

Sagarika Mukesh

Pinping Sun

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.

Composite material phase change memory cell

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Looped long channel field-effect transistor

A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

Self-aligned C-shaped vertical field effect transistor

Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Single-mask alternating line deposition

A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.

Self aligned replacement metal source/drain FINFET

One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Gate-all-around field effect transistor having multiple threshold voltages

A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Top via interconnect having a line with a reduced bottom dimension

An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

Interconnects having spacers for improved top via critical dimension and overlay tolerance

A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Top via with damascene line and via

A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Semiconductor device and method of forming the semiconductor device

A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Top via process with damascene metal

A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Fully aligned top vias

Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Top via with next level line selective growth

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Colchester, VT, United States of America

Robert Russell Robison