3com Corporation

Infineon Technologies Austria Ag

Robert Reissfelder

Heidi R Pickreign

Laxminarayan Krishnamurthy

Glenn William Connery

Scott Wilson Southwell

Mattia Oddicini

John J Platko

David R Lewis

Christopher J Duguay

Robert F Turnbull

Michael K Brown

Paul M Gitahi

Suejong Choi Perranoski

An apparatus includes processing hardware, storage hardware, and serial communication hardware. The processing hardware receives selection of a serial communication protocol. The serial communication protocol is selected amongst multiple serial communication protocols to control operation of a power converter. Via the processing hardware or other suitable entity, the storage hardware is populated with a set of command decode functions (a.k.a., command descriptors) assigned to the selected serial communication protocol. During operation, the serial communication hardware receives commands over a serial communication interface and executes the received commands via the set of command decode functions in the storage hardware. Each of the multiple commands communicated over the serial communication interface is encoded in accordance with the selected serial communication protocol. The serial communication hardware uses the set of command decode functions to execute the received commands.

Flexible high speed interface implementation in a power supply

A system and method for implementing an SMBus/IC interface in a computer connectable to a network. The system includes a plurality of devices communicably coupled to an SMBus. The system operates at a first clock rate when the system is awake, and at a second clock rate less than the first clock rate when the system is sleeping. At least when the system is sleeping, a first device stores data transferred via the SMBus in a register, and a second device drives the clock line of the SMBus to a low logic level while the data is stored in the register of the first device. Upon completion of the data transfer operation, the first device clears the data from the register, and the second device releases the clock line to allow it to be pulled-up by pull-up circuitry connected to the SMBus.

System and method for implementing an SMBus/I2C interface on a network interface card

A system and method of mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space, and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set such that an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address, and transfers the data to the host computer.

Host computer virtual memory within a network interface adapter

The present application is directed to a method and system for mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor contained within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set, such that, an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address and transfers the data to the host computer.

A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor. The master processor effects data transfers from the slave processor to the memory over the data bus by reading a series of data from the slave processor onto the data bus, generating a series of memory addresses as the data are being read from the slave processor, and writing each data word into the memory as it appears on the data bus.

Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory

Growing community of inventors

Westwood, MA, United States of America

Robert Reissfelder