Wang Laboratories, Inc.

Robert R Trottier

James B MacDonald

David L Whipple

Kevin T Mahoney

Stephen W Olson

Peter A Morrison

Dennis J Kayser

Robert C Nash

Tom R Kibler

Bhikoo J Patel

David A Reeder

John M Martins

Andrew N Fu

Robert J Slezak

An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

I/O structure for information processing system

A loosely-coupled computer system certains global resources and is made up of stand-alone systems connected by a data link. Each stand-alone system includes a global identifier list which contains identifiers for global resources and the locations of those resources. The global identifier list in each system is identical to those on other systems. Each system further includes a global identifier list maintenance system, an outbound global resource system, an inbound global resource system, and a communications system. When a request for a global resource is made in a stand-alone system, the outbound global resource system determines whether the resource is local or remote. If the resource is remote, the outbound global resource system makes a resource access message and sends it via the communications system to the remote system where the resource is located. The inbound global resource system on the remote system responds to the resource access message by performing the access and providing a return message to the local system. The global identifier list maintenance system keeps the identifier list identical in all stand-alone systems. Global resources disclosed include global aliases for mailboxes, global file access, and global user and group name lists.

Loosely-coupled computer system using global identifiers to identify

A high speed link used to connect peer computer systems. The link includes data lines and control lines connected to a device adapter in the I/O system of each of the peer computer systems and logic in each device adapter. The data lines carry data words in parallel; the control lines include status lines indicating status of each of the peer systems, arbitration lines for indicating which of the peer systems currently desires to transmit data across the link and whether the link is available, and receiver acquisition lines for specifying which of the peer systems is to receive a transmission and whether the specified system is able to receive the transmission. The logic in the device adapter includes status logic responsive to the status lines for inhibiting a transmission when the receiving peer system is not ready, arbitration logic responsive to the arbitration lines for deciding which peer system may have access to the link at any given time, and receiver acquisition logic permitting the transmitting device adapter to specify the receiving system, permitting the receiving device adapter to return its address and acknowledge its selection, and permitting the transmitting device adapter to verify the selection and determine whether the receiving system is able to receive data.

High-speed link for connecting peer systems

Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality M of memory banks, each having a separate data output path. In a first configuration a memory controller addresses the memory banks sequentially to read from one address location at a time. The memory is reconfigured by an address translator providing addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank output busses as the memory output to the system processor. In a further embodiment, a cache is connected in parallel with the parallel bank outputs for storing information appearing upon the non-selected bank output busses paths for subsequent transfer to the memory output in a subsequent reading from memory of previously read but non-selected information.

Reconfigurable memory system

Growing community of inventors

Lowell, MA, United States of America

Robert R Trottier