Motorola Corporation

Other

Robert R Thompson

David S Mothersole

Douglas B MacGregor

Mark W Bluhm

John Kuban

Lester M Crudele

Jay A Hartvigsen

Robert W Aaron

James L Tietjen

A device attachable to at least one of the co-acting jaws of a steel jawed trap for capturing an animal. The device has at least one cushion assembly that includes an elongated carrier frame attachable to at least one jaw of the trap, and spaced apart cushion members secured to the carrier frame. The cushion members project outwardly from the carrier frame and are in a parallel alignment to one another to engage a limb of the animal and cushion and distribute the force of the jaws of the trap to reduce animal injuries.

Cushion device for animal traps

An animal pelt stretching and drying device that is adjustable for use with differently sized animal pelts includes a pair of spaced apart elongated side members and an inverted 'V'-shaped top member that is adjustably attached to the side members to vary the distance the top member extends above the side members. Also, at least one cross arm member is associated with the side members for controlling the spacing therebetween and can also be adjusted to vary the position of the cross arm member with respect to the upper portions of the side members.

Animal pelt stretching and drying device

A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential V.sub.PP (23). An EPROM control register (53) in the CPU is loadable under the control of a computer program stored in an external memory (40). Responsive to a first bit in the EPROM control register an address buffer/latch 61 and a data latch 62 temporarily latch address and data information during a write operation to the EPROM. Responsive to a second bit in the EPROM control register the programming potential is applied to the EPROM for a predetermined time to program the data information into the EPROM at its associated address. The accuracy of the programming operation may be verified using the CPU under the control of the external computer program, to compare the address and data information programmed into the EPROM with the original source of such information.

Microprocessor having self-programmed eprom

A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.

Microcomputer with change of flow

In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.

Data processor having multiple cycle operand cycles

In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines 'hits' and 'misses', and that the actual instruction cache portion functions accurately.

Microcode testing of PLA's in a data processor

Microcode testing of a cache in a data processor

A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.

Microcomputer which prioritizes instruction prefetch requests and data

An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.

Instruction address calculation unit for a microprocessor

A trap assembly for capturing small animals formed from a housing that encloses a jaw assembly for grasping the paw or leg of the animals. The jaw assembly is formed from a trap plate having an aperture and a resiliently biased arm that is movable from an open position to a closed position where it coacts with side edges of the plate aperture to form a pair of jaws for grasping the animal.

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Austin, TX, United States of America

Robert R Thompson