Altera Corporation

Robert R N Bielby

Chiakang Sung

Joseph Huang

Bonnie I Wang

Richard G Cliff

Edward Aung

Myron Wai Wong

Krishna Rangasayee

John C Costello

Mark W Fiester

W Bradley Vest

A programmable logic device is provided with phase-locked loop (&ldquo;PLL&rdquo;) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

Phase-locked loop circuitry for programmable logic devices

A programmable logic device is provided with phase-locked loop (&ldquo;PLL&rdquo;) or delay-locked loop (&ldquo;DLL&rdquo;) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Phase-locked loop or delay-locked loop circuitry for programmable logic devices

An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (,) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (,) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

Reducing I/O noise when leaving programming mode

A programmable logic device is provided with phase-locked loop (&ldquo;PLL&rdquo;) or delay-locked loop (&ldquo;DLL&rdquo;) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

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Pleasanton, CA, United States of America

Robert R N Bielby