Bell Telephone Laboratories

Bell Communications Research, Inc.

Tellium, Inc.

Robert R Cordell

Gee-Kung Chang

Krishna Bala

Paul Grabbe

James John Ringo

A wavelength-interchanging cross-connect for a wavelength-division multiplexing (WDM) optical communication system including both transparent optical paths and opaque paths through an electronic switching network, such as a high-speed digital cross-connect switch (DCS), including matching opto-electronic conversions of the data signal. All-optical switching is performed on the input and output sides, for example, by mechanically actuated fiber switches. The DCS, receiving optical inputs from the input optical switches and providing optical outputs to the output optical switches, performs switching in the electrical domain and can perform wavelength conversion of the signals passing through it. The DCS also provides for access to electrical add/drop lines for interfacing to a client. The transparent optical path, which can be either direct or through an optical switch, transfers a signal without regard to its format from the input to the output of the switching system. An algorithm is available for setting up the required connection through the different components.

Hybrid wavelength-interchanging cross-connect

A multi-wavelength optical receiver including multiple photodetectors receiving different ones of a multi-wavelength signal. For each wavelength-dedicated photodetector, a separate electronic receiver circuitry is provided including a current-to-voltage converting input transistor and an emitter-follower output transistor arranged as an operational amplifier with a feedback resistor. The circuit is improved by a cascode connection to the input transistor, by a reference to an analog ground rather than to a power supply line in both the photodiode and the cascode transistor, by the addition of capacitive shunts and a clamping transistor parallel to the feedback resistor in the feedback loop from the output transistor to the input transistor, by including positive and negative power supplies for the input and the output stages, by including multiple emitter followers in the output, by use of a differential second stage referenced to the analog ground, and by use of an output matching network that makes use of parasitic packaging inductances. Thereby, noise is reduce and inter-channel interference is minimized.

Optical receiver particularly useful for a multi-wavelength receiver array

A method and a system for routing cells in an ATM switch. The switch which is input buffered, employs a multiplicity of crosspoint switch planes operating simultaneously in parallel, and whose outputs are combined by an output-buffered second stage. A traffic controlling or path assignment switching stage disposed before the crosspoint switch planes improves performance in the presence of correlated traffic. The switching stage may either control the traffic randomly or adaptively. Input concentration and output expansion functions within the switch are also disclosed. The use of an 'unfair' or a predictable preference contention resolution device (CRD) in each of the crosspoint switch planes is possible in another embodiment of the invention. Advantages of the method and system include linear growth with large N in the size and complexity of both the switching circuits and the contention resolution circuits. Switch performance tends to gracefully degrade with failures in switch planes and contention resolution devices. Dense, low-cost memory with simple FIFO addressing schemes can be used to realize both the input and output buffered stages.

Method and system for routing cells in an ATM switch

A variable word length (VWL) decoder is disclosed in which an input bit stream of variable length words is input to a programmable logic array (PLA) (305) through an input shift register (302). The data association input plane (306) of the PLA compares the sequence of input bits in the register with all the possible variable length words. When a match is made, the PLA's length output plan (307) produces an output word representing the length of the detected variable length word and the PLA's word output plan (308) produces the fixed length word corresponding to the input VWL word. This fixed length word is input to a latch which is controlled by a downcounter (311). The length word is loaded into this downcounter, which decrements its count as the input bits are shifted through the register. Only when its count reaches zero have all bits of the previous variable length word been clocked through the shift register. Therefore, only on the count of zero does the output of the word output plane represent a fixed length word that properly corresponds to a valid VWL input word. Thus, only on the count of zero is the latch enabled to transfer to its output the word then at the output of the word output plane. The feedforward only architecture of the VWL decoder does not require any information regarding the decoded word length to be fed back to the input. This architecture is therfore not limited by speed constraints that would otherwise exist if the length of each decoded word needed to be fed back to the input before the next word could be decoded.

High-speed feedforward variable word length decoder

The circuit phase aligns a phase-varying input data stream with a local clock. The data stream is sampled at the 0.degree. and 180.degree. phases of the local clock. Two pairs of outrigger samples which closely bracket the aforementioned primary samples are also obtained by the sextet sampler. Adjacent pairs of the six samples are applied to Ex-Or gates to yield disagreement signals which indicate the locations of data transitions relative to the samples. The primary samples (0.degree. and 180.degree.) are serially loaded into different halves of a biphase register, the taps of which provide the output with differently delayed versions of the input data at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals to a counter which determines which of the biphase register taps is connected to the output. The output is a replica of the input which is synchronized with the local clock.

Digital phase aligner with outrigger sampling

A Phase/Frequency Locked Loop comprises a controllable oscillator which is phase locked with the clock of an incoming non-return-to-zero digital data signal. The controllable oscillator may be a voltage-controlled oscillator (VCO) or may be purely digital. The circuitry includes a novel digital phase and frequency detector which detects both frequency and phase error by sampling the incoming data stream at multiple phases of the output of the VCO (or the digital equivalent thereof). One of two binary disagreement signals are produced depending on the sense of the phase error. During periods of frequency error, the circuit automatically selects the proper type of disagreement signal (the leading-edge disagreement) required to achieve frequency lock.

Phase and frequency detector circuits

This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0.degree.) and anti-phase (180.degree.) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.

Digital phase aligner

An integrated circuit current source (10) has first (16) and second (30) current mirrors regeneratively coupled. The transistors (32, 34) of the second mirror (30) have unequal current densities, so that a resistor (40) connected to the emitter of the lower current density transistor (34) establishes a temperature-dependent output current. One of the transistors (18, 20, 34) has its base and emitter connected together through a modifying resistor (42, 53, 55) to modify the temperature dependence of the output. In one embodiment (10), the modifying resistor (42) connects the base and emitter of the lower current density transistor (34) and increases the temperature dependence of the output to make it directly proportional to the absolute temperature. Other embodiments (52, 54) are disclosed for obtaining both zero and negative temperature coefficient values for the output.

Current source with modified temperature coefficient

An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape. A circuit interconnects with input and output terminals for combining input and output signals into an intermediate signal having a magnitude equal to a weighted sum of the input and output signals. A frequency dependent circuit responds to the intermediate signal for producing a frequency dependent signal that is combined with the input signal to generate the output signal.

Active variable equalizer

An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.

A family of window comparator circuits are arranged to monitor differential input signals and indicate when the difference between the signals is between two limits. Each of the window comparator circuits includes an input circuit having at least one current source. The input circuit is responsive to a differential input signal for conducting two dependently variable currents through an output circuit. At least one voltage dropping element is connected to each current source in the input circuit for establishing the limits of the window comparator. The output circuit responds to changes in the ratio between the two currents conducted therethrough for indicating that the differential input signal is between the two limits.

Window comparator

A narrow-band tone decoder has a controllable oscillator, connected in a fast-capture phase-locked loop, for generating a signal having a frequency determined by a control signal produced within the loop. A synchronous detector, which responds to an input signal of the tone decoder and to a signal from the controllable oscillator, produces a signal having a magnitude dependent upon the magnitudes of the input signal and of the signal from the controllable oscillator. A window comparator monitors the control signal within the loop for deciding when the generated signal is within a predetermined frequency range.

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Tinton Falls, NJ, United States of America

Robert R Cordell