Cadence Design Systems, Inc.

Robert Pierce

Robert Alan Reid

Narayanan Vinay Krishnan

Amit Bhardwaj

An invention is provided for wear leveling in a non-volatile memory system utilizing relative wear counters to indicate relative levels of wear for each memory block in a non-volatile memory system. Whenever a memory block is erased, the associated relative wear counter is incremented. Then, when any relative wear counter reaches a predetermined limit, the value of the lowest relative wear counter is subtracted from each relative wear counter. Thus, each relative wear counter indicates a relative wear level of the associated memory block relative to other memory blocks. In this manner, the relative wear levels are maintained while reducing the amount of memory needed to for each relative wear counter.

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Danville, CA, United States of America

Robert Pierce