Sgs-thomson Microelectronics S.a.

Stmicroelectronics S.a.

Stmicroelectronics Gmbh

Sgs-thomas Microelectronics S.a.

Robert Pezzani

Eric Bernier

Bertrand Rivet

Fabrice Guitton

Denis Berthiot

Albert Senes

Angelo Ugge

A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.

HF-controlled SCR-type switch

A constant current generator connected between first and second terminals includes a gate turn-off thyristor in series with a resistor; a current limiting component connected between the anode gate and the cathode gate of the thyristor; and a voltage reference connected between the cathode and the cathode gate of the thyristor.

Constant current generator

The invention relates to a vertical-type power switch disposed in a semi-conductor chip, comprising a winding () located on the periphery of at least one face of said chip. Said winding comprises two binding posts () which supply a signal that is proportional to the current fluctuations in said switch.

Di/dt servo power switches

A capacitive microsensor formed on a wafer, including a conductive detection area arranged on a first surface or front surface of the wafer; a conductive via crossing the wafer and emerging on said area; and a structure to ensure contact with said via on the second surface or rear surface of the wafer.

Capacitive microsensor

The invention concerns a control circuit for controlling a power switch by means of a galvanic insulation transformer, the transformer being produced in the form of planar conductive windings on an insulating substrate () whereon are integrated passive components constituting a high frequency excitation oscillating circuit for a primary winding of the transformer, the transformer substrate being directly mounted on a wafer () whereon is mounted a circuit chip () integrating the power switch.

Integrated switch with RF transformer control

A clipping device intended for absorbing current peaks from 1 to 10 amperes, formed of a vertical NPN transistor, having an unconnected base, an emitter connected to a terminal on which positive voltage peaks are likely to appear, and a grounded collector, the transistor parameters being set so that it exhibits a negative dynamic resistance.

Clipping device with a negative resistance

A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Electrical control methods involving semiconductor components

The invention concerns a control circuit for controlling a load to be supplied in alternating current voltage, comprising a two-way switch capable of being controlled by phase angle, in series with the load between two terminals applying the alternating current supply, and comprising, in parallel with the switch, a first resistive element, a first capacitor and an element, in series with the first resistive element and the first capacitor, and operating, in steady state conditions, as a constant current source, the midpoint of the association in series connection of the first resistive element and the first capacitor being connected, via an element with two-way conduction automatically triggered when the voltage at its terminals exceeds a predetermined threshold, to a terminal controlling the switch.

Circuit for controlling a load to be supplied by an alternating current voltage

The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.

Network of triacs with gates referenced with respect to a common opposite face electrode

Power integrated circuit

A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.

Overvoltage protection circuit

Network of triacs with gates referenced with respect to a common

Method for making power integrated circuit

A monolithic component including, in an N-type lightly-doped substrate of a semiconductor wafer, two portions separated by a P-type insulating wall. A first portion of the two portions includes a high voltage lateral component, a layer of which substantially corresponds to the thickness of the wafer. The second portion includes logic circuit components. A rear surface of the substrate includes a P-type layer coated with a metallization. The insulating wall is in electrical contact with a low voltage terminal of the high voltage lateral component, such as the gate region of a thyristor. The logic portion includes at least one vertical component.

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Vouvray, France

Robert Pezzani