Linear Technology Corporation

Robert Peter Jurgilewicz

Roger A Zemke

Victor F Fleury

Jeffrey Lynn Heath

An apparatus and method for event synchronization. One or more devices that have a plurality of events to be carried out in a scheduled order in time are connected to a single shared time position clock (TPCLK). There are one or more sequencing controllers coupled with the one or more devices and configured to control the timing of high and low states of the shared TPCLK in accordance with the scheduled order. The synchronization among the plurality of events in the scheduled order is achieved based on the high and low states of the shared TPCLK and such synchronization of the plurality of events in the scheduled order is operated without the presence of master and slave devices.

Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments

Novel system and protocol for controlling a sequence of events. The sequencing system has a master circuit for providing sequencing information defining a sequence of events using a sequencing signal, and at least one slave circuit responsive to the sequencing signal for producing at least one event signal defining an event. The master and slave circuits are configured for providing a bidirectional transfer of the sequencing information via a single wire.

Single-wire sequencing technique

A system for monitoring multiple power supply signals with respect to a threshold has multiple inputs for receiving input power supply signals. A processing circuit of the system produces an output signal at a first level when the power supply signals have a prescribed relationship to a threshold value, and produces the output signal at a second level when at least one of the input power supply signals does not have the prescribed relationship to the threshold value. The processing circuit is configured for selecting the first level corresponding to a level of an input power supply signal at a pre-selected one of the inputs.

Multi-input power supply supervisor

A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be pulled-up to a logic HIGH voltage, for example, by removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor. A low voltage pull-down circuit may be provided in a power supervision circuit for systems that operate with, for example, low power conditions. The open-drain node is utilized as a power-on-reset node that provides a LOW logic signal to a system when the power being supplied to the system is below a predetermined voltage threshold.

Low voltage pull-down circuit

A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be easily pulled-up to a logic HIGH voltage, for example, by simply removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor.

Growing community of inventors

Pepperell, MA, United States of America

Robert Peter Jurgilewicz