Other

International Business Machines Corporation

Oracle International Corporation

Oracle America, Inc.

Transmeta Corporation

Fujitsu Corporation

Intellectual Ventures Holding 81 LLC

Fujistu Limited

Intellectual Venture Funding LLC

Robert Paul Masleid

James B Burr

John Stephen Muhich

Scott Pitkethly

Anand Dixit

David J Greenhill

Michael Pelham

Jason M Hart

Vatsal Dholabhai

Ali Vahidsafa

Steven Thomas Stoiber

Larry Bryce Phillips

Daniel Mark Dreps

Guillermo Juan Rozas

Paul N Loewenstein

Kleanthes G Koniaris

Hanh-Phuc Le

Christophe Giacomotto

George McNeil Lattimore

Andre Kowalczyk

Akihiko Harada

Thirumalai Swamy Suresh

Donald George Mikan, Jr

Michael Kevin Ciraula

Parsotam Trikam Patel

Georgios K Konstadinidis

Alex Klaiber

Aparna Ramachandran

Stephen Phillips

Don Draper

Amy May Tuvell

Duncan C Collier

Christian Klingner

Venkat Krishnaswamy

Kenny C Gross

Wolfgang Roesner

David K McElfresh

Alexander Klaiber

Sebastian Turullols

John Beck

Martin Stanley Schmookler

Ramakrishna C Dhanekula

Israel A Wagner

Gregory Stuart Scott

Paul S Serris

John P Banning

Thomas R Toms

Byron Lee Krauter

Nandor G Thoma

Ilyas Elkin

Bidyut Kanti Sen

Sanjiv Kapil

Heechoul Park

James Ballard

Changku Hwang

David Roger Ditzel

Sadar U Ahmed

Ha Pham

Gurmeet Singh

Paul J Dickinson

David James Martens

Alan Smith

Sreemala Pannala

Robert F Sechler

King Cheung Yen

Karl P Dahlgren

Johan Bastiaens

Murali M R Gala

Tiberiu Carol Galambos

Georgios Konstadinidis

Hoki Kim

Venkata Kottapalli

Eben Kunz

Laura Kocubinski

James Van Zoeren

Michael L Cooper

Zhirong Feng

Bijoy Kalloor

Jose Sousa

King Yen

Christopher Giacomotto

Donald Arthur Draper

Alan P Smith

On-die functional blocks may use multiple communication networks to send requests and receive responses. For example, a first functional block may send a request via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

Multiple on-die communication networks

Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Body-bias voltage routing structures

A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power(PWR) bump pad within a PWRbump region, a VSS bump pad within a VSS bump region, and a power(PWR) bump pad within a PWRbump region. The metal-top layer may also include a PWRmajority metal-top region. The MFDM may also include a metal-top-layer beneath the metal-top layer and including a VSS majority metal-top-region, a PWRmetal-top-region, and a PWRmetal-top-region. The MFDM may also include a metal-top-layer beneath the metal-top-layer and including a PWRmajority metal-top-region, a VSS metal-top-region, and a PWRmetal-top-region. The MFDM may also include top-VIAs disposed between the metal-top layer and the metal-top-layer, and top-VIAs disposed between the metal-top-layer and the metal-top-layer.

Multi-layer full dense mesh

An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

Digital encoding of parallel busses to suppress simultaneous switching output noise

A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Cross point switch

Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular 'quads.' The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other.

Low-noise arrangement for very-large-scale integration differential input/output structures

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Power efficient multiplexer

A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Rotational synchronizer circuit for metastablity resolution

An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

Variable run length encoding of a bit stream

Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

Codec to reduce simultaneously switching outputs

Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design.

Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain

An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.

Coarse data aligner

Growing community of inventors

Monte Sereno, CA, United States of America

Robert Paul Masleid