Lucent Technologies Inc.

Cadence Design Systems, Inc.

Bell Telephone Laboratories

At+t Corp.

At&t Bell Laboratories

Agere Systems Inc.

Robert Paul Kurshan

Ronald H Hardin

Xiaoqun Du

Kavita Ravi

Kenneth L McMillan

Carlos Manuel Roman

David Malah

Bhaskarpillai Gopinath

Alok Jain

Manu Chopra

Doron A Peled

Marius Minea

Vladimir Levin

Husnu Yenigun

David Hertz

Ravi Prakash

Mihalis Yannakakis

Franz Erich Marschner

Rajeev Alur

Pratik Mahajan

Zvi Har'El

Alon Itai

Glenn R Wesley

Arthur Barry Glaser

Gary F De Palma

Frederic Doucet

Kedar Sharadchandra Namjoshi

An improved approach for designing and verifying electronic designs at different levels of abstractions is disclosed. An electronic design undergoes high level verification, where the results of the high level verification can be guaranteed to be correct at the RTL level. This can be implemented by ensuring that model consistency rules are followed to generate high level (enhanced transaction level) models and/or RTL data. In this way, properties that are verified at one level of abstraction will not need to be re-verified at the other level of abstraction.

Method and system for performing verification of an electronic design

Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as 'top-down' design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.

Method and system for implementing top down design and verification of an electronic design

Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as 'top-down' design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design.

Method and system for implementing top down design and verification of an electrical circuit design

A method of electronic circuit design includes performing property verification for partitions of a design of an electronic circuit, selecting an outcome for each partition from a plurality of outcome categories, and computing coverage information for each element of the design based on the outcome.

Coverage metric and coverage computation for verification based on design partitions

A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated within the circuit design. The circuit design is then verified using at least one of the propagated assertions as an assumption.

Method and system for verifying circuit designs through propagation of assertions

A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.

Method and system for partitioning an integrated circuit design

In testing a system, coverage of the testing is obtained by maintaining a store of information that is populated as the testing progresses. The store maintains information about the ranges of system variables that are employed during the testing. At the conclusion of the testing, the coverage of the testing is reported out, to permit the designer to assess whether other queries ought to be formulated, or whether portions of the system are superfluous. The testing can employ simulations, formal verifications, or some other techniques.

Verification coverage method

A method for checking on cyclicity of a set of definitions employs a simple, non-computational definition of constructivity and a symbolic algorithm based on the new, simple to implement, formulation for variables with arbitrary finite types. This is accomplished by extending variable type to include the &ldquo;undeterminable&rdquo; value &perp; (read as &ldquo;bottom&rdquo;). This formulation is non-computational and easily extensible to variables with any finite type. The formulation also handles definitions of indexed variables in the same manner. The set of definitions is then checked to determine whether any of the variables assume the value is &perp;.

Method for identifying cyclicity in circuit designs

Efficient formal verification of a system model is obtained by performing a state reachability analysis of an unrestricted full system model that includes constraints selected by the tester for testing a given property, followed by an analysis that permits a reduction in the complexity of the tested system's model. The analysis involves determining variables of the system's model that do not change value in the course of the state reachability analysis, often because of the constraints imposed prior to performing the reachability analysis. The unchanging variables are replaced with constants, and those constants are propagated through the system model to simplify the state transition relations that define the system. The simplified system model is then applied to a verification tool to determine whether the liveness property is satisfied.

Detecting of model errors through simplification of model via state reachability analysis

A static partial order reduction generator and process result in a substantially reduced state space graph of a multi-process system, independently of the model checking process. The process of this invention creates a modified state graph generator with appended rules that allow any desired state searching tactic (breadth first, depth first, etc.) to be employed when states and transitions are considered in the course of verification. This permits use of existing model checking tools without needing to modify them. The static partial order reduction is made possible by realizing that a prior art condition that at least one state along each cycle of the reduced state graph must be fully expanded can be guaranteed by considering the individual processes that make up the system and identifying certain transitions in those processes.

Static partial order reduction

A method and apparatus that employs static partial order reduction and symbolic verification allow the design of a system that includes both hardware and software to be verified. The system is specified in a hardware-centric language and a software-centric language, as appropriate, and properties are verified one at a time. Each property is identified whether it is hardware-centric or software-centric. A hardware-centric property that contains little software is does not employ the static partial order reduction. Software-centric properties, and hardware-centric properties that have substantial amounts of software do employ the static partial order reduction. Following partial order reduction, the software-centric language specifications are converted to synchronous form and combined with the hardware-centric specifications. The combined specification is applied to a symbolic verification tool, such as COSPAN, and the results are displayed.

Verifying hardware in its software context and vice-versa

Verification systems which employ automata-theoretic formal verification use a model automaton made from a system process (,) representing the system and a task automaton (,) representing the task and use the model automaton to test (,) whether the language of the system process is contained in the language of the task automaton. An improved technique reduces the computational complexity of the language containment testing by producing a model (,) which represents a system which has been automatically localized with regard to a task. Another technique reduces the computational complexity of stepwise refinement (,). In stepwise refinement, the system automaton is refined a step at a time until it reaches the complexity of a practical implementation. The computational complexity of the stepwise refinement is reduced by a technique which permits language containment to be tested using a set of models made from process-automaton pairs rather than process-process pairs.

Automata-theoretic verification of systems

A method wherein a verification tool checks the properties of a system model by performing a partial search of the system-model state space. A partial search is a search wherein the verification tool inputs, at each state of the system-model state space, only a subset or fraction of the complete set of inputs that would have been used during a conventional search. Performing a partial search, instead of a conventional search, reduces the total number of inputs that the verification tool will input to the system model during a search of the system-model state space, thus reducing the amount of computational resources and/or time needed by the verification tool to verify given properties of the system model. Moreover, performing a partial search, instead of a conventional search, does not substantially reduce the ability of the verification tool to identify errors in the system-model.

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New York, NY, United States of America

Robert Paul Kurshan