Hamilton Sundstrand Space Systems International, Inc.

Hamilton Sundstrand Corporation

Robert P Wichowski

Kevin G Hawes

Patrick J Sears

Timothy A Roberts

Harold J Hansen

W Clark Dean

Darren Woodman

Sean K Murray

Diego S Mugurusa

Thinh Pho

Nicholas Van Derzee

Michael A O'Toole

Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems.

Reconfigurable stand alone distributed system motor controllers

Diagnosing whether controllers of internal vehicle systems are the source of failures detected by a system control managing a vehicle such as a spacecraft. Highspeed data is received via at a field programmable gate array (FPGA) embedded in an assembly of the vehicle. The FPGA includes a controller and a digital diagnostic interface. In one embodiment, the diagnostic interface utilizes Very Highspeed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for performance modeling of a controller configured to control at least one internal system within the vehicle. The VHDL performance models the controller. Upon receiving an indication of a failure, the performance modeling of the controller is used to ascertain whether or not the controller is the source of the failure. Disassembly of the assembly housing the internal system is not required in order to ascertain whether or not the controller is the source of the failure.

Highspeed data interface for distributed system motor controllers

Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.

Shared resistive sensor measurement with FPGA based collision avoidance protection

A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

Digital motor controller stability analysis tool

A counter is started on the falling edge of a tach pulse. This counter counts to the rising edge of a second tach pulse, such as the next tach pulse. During the duration of the tach pulse the FPGA calculates the RPM of a motor. In this way, during each commutation period, a RPM is calculated. The present system performs a RPM calculation during each commutation period and/or tach pulse duration.

Field programmable gate array based brushless DC motor speed detector

A system for detecting sensor failure and/or operating with a failed sensor in an electrical machine includes an electrical machine, three or more sensors configured to connect to the electrical machine, and a sensor module operatively connected to each sensor to receive sensor signals from the sensors. The sensor module includes a failure detection module operatively connected to each sensor and configured to determine if each sensor is a failed sensor or a functioning sensor. The sensor module also includes a virtual sensor module operatively connected to the failure detection module and configured to output simulated sensor signals for the failed sensor, wherein the sensor module is configured to output the sensor signals for each functioning sensor. The system includes a control module operatively connected to the sensor module and the electrical machine to receive sensor signals and simulated sensor signals to control operation of the electrical machine.

Sensor and control systems for electrical machines

A system includes a first control system configured to operate at a first clock speed, a second control system configured to provide an output to the first control system and configured to operate at a second clock speed different from the first clock speed, and a synchronization module operatively connecting the first control module to the second control module and configured to synchronize the first control system and the second control system such that the output of the second control system is timed to synchronize with the first clock speed.

Synchronization module for motor speed control

A sensorless motor controller includes a variable link control, including a radiation-hardened field programmable gate array (FPGA) and a back electromotive force (EMF) decoder circuit. The back EMF decoder infers the position of a rotor of the motor. A filter on the decoder conditions the back EMF signal and has multiple cutoff frequencies which can be dynamically controlled by the FPGA in order to compensate for phase shift in the back EMF signal. The FPGA also controls a variable DC link and its digital speed control loop.

Variable link sensorless brushless direct current motor controller for space and hardened applications

A compact field programmable gate array (FPGA)-based digital motor controller (), a method, and a design structure are provided. The compact FPGA-based digital motor controller () includes a sensor interface () configured to receive sensor data from one or more sensors () and generate conditioned sensor data. The one or more sensors () provide position information for a DC brushless motor (). The compact FPGA-based digital motor controller () also includes a commutation control () configured to create switching commands to control commutation for the DC brushless motor (). The commutation control () generates commutation pulses from the conditioned sensor data of the sensor interface (). The compact FPGA-based digital motor controller () also includes a time inverter () configured to receive the commutation pulses. The time inverter () converts the commutation pulses into a rotational speed of the DC brushless motor () to provide a linear feedback control parameter.

Compact FPGA-based digital motor controller

A body armor assembly includes a plurality of rigid tiles that are supported in a manner to provide movement and flexibility while still providing the protection of rigid armor. In a disclosed example, a tile holder maintains a plurality of tiles in a selected alignment. The tile holder maintains a minimum overlap dimension between adjacent tiles. Some of the tiles are maintained by the tile holder in a manner that allows for the overlap dimension to increase beyond the minimum overlap dimension. In a disclosed example, at least two rigid layers have at least one ballistic material layer between them to provide a rigid armor material composition.

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Westfield, MA, United States of America

Robert P Wichowski