Wang Laboratories, Inc.

3com Corporation

Robert P Ryan

Kin L Cheung

John A Flanders

William D Townsend

Stephen L Van Seters

David C Ready

Paul J Giacobbe

Leonard Schwartz

John B Crowther

Ryan T Ross

Robert A MacDonald

A clock crossing FIFO capable of functioning regardless of relative clock frequencies on the write and read sides. Toggle signals are utilized to cross the clock boundaries. The number of write counts which have been accrued but not acknowledged by the read side are tracked, and this number is stored as of the issuance of a write toggle. Upon toggle receipt on the read side, this number is latched as a measure of the number of data units which can be read from the FIFO. At the same time, the toggle is returned to the write side for decrementing the number of write counts outstanding by the number conveyed to the read side. Similar circuitry is employed for conveying to the write side circuitry the number of data units which have been read by the read side circuitry. The presently disclosed FIFO and associated circuitry operates independent of relative clock speeds, and the particular size of the FIFO is scalable.

Frequency independent asynchronous clock crossing FIFO

Logic circuits are employed in a telecommunications bridge/router device to examine a received frame to determine which VLAN, if any, the frame is associated with. The protocol type, receive port identification, and receive VLAN tag are employed to determine the transmit port identification and transmit VLAN tag. A predefined table indicates which ports within the bridge/router are associated with the VLAN. The frame is excluded from transmission through the ports that are not associated with members of the respective the VLAN.

Method and apparatus for VLAN support

Apparatus for use in a multi-CPU data processing system (10) wherein each CPU (12-18) is coupled to a common bus (20) and through the common bus to a main memory (28). The apparatus provides a program, such as an operating system, that is operating upon each of the CPUs access to a page of data within the main memory. Each of the CPUs generates a first address for identifying a memory location or locations within a page of the main memory. The first address is modified as a function of the first address and as a function of an identification of the CPU to generate a second address for identifying a memory location or locations that are either within the same page or within another page of the main memory. The modified second address is applied to the memory for accessing the memory location or locations.

Apparatus for managing page zero accesses in a multi-processor data

In a multi-processor virtual memory system 10 a Reference and Change Table (RCT) 36 is located upon a Memory Control Unit (MCU) 25. The RCT 36 is responsive to accesses to any of the Memory Modules (MMs) 24-26 and generates and maintains status bits indicative of the reference and change activity of all of page frames of the system memory that are accessible by any of the CPUs 12A-12n. In that each of the CPUs 12A-12n has access to the page frames of the system memory each of the CPUs 12A-12n is further enabled, via privileged instructions, to test (read) and reset (clear) over a system bus 16 the memory page frame status bits that are generated and stored by the RCT 36. As such, the RCT provides to multiple data processors a centralized and readily accessible store of status information relating to page frames of the system memory.

Reference and change table storage system for virtual memory data

A distributed reference and change table 36 for a virtual memory system 10 has a number of storage locations at least equal to the maximum number of data blocks of an associated read/write physical memory. A memory module 24 has a plurality of data words organized into n number of data blocks. The memory module includes an integral reference and change table having at least n storage locations each having at least two bits, one bit indicating the occurrence of an access (reference) to a corresponding data block and the other bit indicating if the access was a write (or change) type of access. A plurality of such memory modules are physically and electrically coupled to a common memory carrier module, each of the plurality of memory modules having an integral reference and change table.

Growing community of inventors

Marlborough, MA, United States of America

Robert P Ryan