Intel Corporation

Robert P Knight

Hong Wang

Xiang Chris Zou

Robert Geva

Ittai Anati

Gautham N Chinya

Chris J Newburn

Dion Rodgers

Bryant E Bigbee

Gautam Upadhyaya

Min Yeol Lim

Neha Sharma

Per H Hammarlund

Scott Dion Rodgers

John P Shen

Jim B Crossland

Aaron N Levinson

Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Power state transition analysis

Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Techniques for tracing wakelock usage

Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

System to profile and optimize user software in a managed run-time environment

In one embodiment, a method includes, upon occurrence of multiple power state transition events for a core of a multi-core processor, reading a value of a system counter of the core and values of low power counters of the core, without expiration of a timer or triggering of an interrupt. These values can be stored in a storage of the processor. Then, after collection is completed, the storage can be accessed to determine a power profile of the processor using the stored values. Other embodiments are described and claimed.

Obtaining power profile information with low overhead

Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.

Programmable event-driven yield mechanism

In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.

Dynamically migrating channels

Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed via a service routine base pointer (SRDS) and a service routine offset value (SRDBP) to obtain the address of a yield service routine via a service routine instruction pointer (SRIP) and a service routine code segment (SRCS). Other embodiments are also described.

Asynchronous control transfer

A system and method are described for configuring and collecting performance counter information of a computer system. The method includes providing one or more performance objects, each object containing a predetermined set of events. A user is allowed to select the entire set or a subset of events to be monitored during a collection session from the predetermined set of events contained in the performance objects. The performance counters associated with the subset of events selected are programmed to increment in response to an occurrence of a respective event. The data stored in each of the performance counters associated with the subset of events selected is periodically read during the collection session.

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Mahomet, IL, United States of America

Robert P Knight