Raytheon Company

University of Illinois

Acumen Scientific

Robert P Ginn

Kenneth Allen Gerber

J Gary Eden

Clark J Wagner

Paul A Tchertchian

Andreas Hampp

Joan K Chia

Stephen H Propst

Steve Solomon

Alexander C Childs

Preferred embodiments of the invention provide semiconducting microcavity plasma devices. Preferred embodiments of the invention are microcavity plasma devices having at least two pn junctions, separated by a microcavity or microchannel and powered by alternate half-cycles of a time-varying voltage waveform. Alternate embodiments have a single pn junction. Microplasma is produced throughout the cavity between single or multiple pn junctions and a dielectric layer isolates the microplasma from the single or multiple pn junctions. Additional preferred embodiments are devices in which the spatial extent of the plasma itself or the n or p regions associated with a pn junction are altered by a third (control) electrode.

Semiconducting microcavity and microchannel plasma devices

A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.

Method of construction of CTE matching structure with wafer processing and resulting structure

InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts. Forming the AlInSb passivation layer before the photodiode detector regions reduces the number of defects created in the n-type InSb substrate during fabrication in comparison to conventional methods and improves the noise performance of InSb photodiodes and sensor arrays incorporating the improved passivation layer.

Infrared photodiodes and sensor arrays with improved passivation layers and methods of manufacture

This invention pertains to a method for processing readout integrated circuits, and to a readout integrated circuit (10) that is processed in accordance with the method. The method includes a first step of providing a plurality of individual readout circuits each having a substrate (12) and at least one layer (14) constructed to have active circuitry that overlies a first surface (12a) of the substrate. Each of the readout integrated circuits has an associated amount of non-flatness or bowing due at least in part to a first force exerted on the substrate by the at least one layer of circuitry. A next step sorts the plurality of readout integrated circuits into a plurality of groups (A, B, C), wherein members of a group have a similar amount of non-flatness. A next step of the method determines, for each group, a thickness of compensating layer (18) and then applies the compensating layer on a second surface (12b) of the substrate so as to exert a second force on the substrate to counteract the first force and to reduce the amount of non-flatness. In a presently preferred embodiment of the invention the step of applying includes a step of sputtering a layer comprised of Si.sub.3 N.sub.4 upon the second surface. The step of sorting includes the steps of operating an interferometer to generate a pattern of fringes for indicating a degree of non-flatness of each of the readout integrated circuits; and counting the fringes and sorting the readout integrated circuits as a function of the number of fringes.

Readout backside processing for hybridization

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Ventura, CA, United States of America

Robert P Ginn