Motorola Corporation

Other

Robert P Dixon

Walter C Seelbach

Randall C Gray

Paul T Bennett

Scott G Nogle

Golnaz Kaveh

A current limit circuit (10/40) for controlling a power transistor (12) has been provided. The current limit circuit includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor for providing an appropriate voltage at the gate electrode of the power transistor when a load is de-coupled from the power transistor. This has the effect of preventing excessive transient current when the load is subsequently coupled to the power transistor. Additionally, the current limit circuit includes circuitry for limiting the current flowing through the power transistor via a sense circuit when the load is coupled to the power transistor.

Current limit sense circuit and method for controlling a transistor

A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power transistor. However, once the power transistor is turned on, the first stage becomes inactive and a second stage (16) coupled to a second supply voltage terminal provides a low current drive signal to the power transistor for fully enhancing the power transistor and lowering its on resistance. The gate drive circuit further includes a timer circuit (18) for rendering the first stage active for predetermined period of time.

Two stage gate drive circuit for a FET

A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.

BICMOS sense circuit for sensing data during a read cycle of a memory

A BiMOS voltage reference circuit which includes a bandgap circuit for providing a predetermined voltage at an output of the circuit that is independent of temperature. A start-up and bias circuit coupled to the bandgap circuit for providing a start-up current to the bandgap circuit during power-up and for providing a bias current to the bandgap circuit after power-up. A feedback circuit coupled to the bandgap circuit for maintaining the bias current to the bandgap circuit independent of power supply variations wherein the predetermined voltage at the output of the circuit is also independent of power supply variations as well as temperature.

Voltage reference circuit with power supply compensation

A circuit is provided that generates a predetermined regulated voltage between first and second terminals that is positioned between first and second power supply voltage rails wherein the predetermined regulated voltage is substantially independent of temperature and power supply variation. The circuit includes a bandgap circuit for providing a predetermined reference potential that is substantially independent of temperature and power supply variation. A resistive circuit provides first and second voltages which are referenced with respect to the first supply voltage rail. A level translator circuit translates the second voltage provided by the resistive circuit to a third voltage which is referenced with respect to the second supply voltage rail. First and second operational amplifier circuits are provided for respectively transferring the first and third voltages respectively to first and second terminals wherein a voltage developed between the first and second terminals is substantially equal to the predetermined reference voltage of the bandgap circuit.

Voltage regulator and method for submicron CMOS circuits

A voltage translator circuit is responsive to applied ECL input signals for providing corresponding CMOS level logic output signals therefrom. The voltage translator circuit includes a pair of substantially identical translator circuits each having an input coupled to an input of the voltage translator circuit and which are supplied a regulated voltage such that the operation thereof is substantially independent of negative power supply variations and temperature. An output stage is coupled between the output of one of the pair of translator circuits and the output of the voltage translator circuit while the output of the other translator circuit is coupled to the output of the voltage translator circuit in order to provide the CMOS level logic output signals.

ECL to CMOS logic translator

A high speed voltage translator provides a CMOS output signal in response to an ECL input signal which is applied to an input stage coupled between first and second power supply conductors wherein the potential developed at the output of the input stage is independent of variations in the power supply voltage. The translating stage is coupled between said first and second power supply conductors and is responsive to the potential developed at the output of the input stage for conducting a predetermined current therethrough. A feedback signal proportional to the magnitude of the predetermined current flowing through the translating stage is generated to control the potential developed at the output of the input stage so as to maintain the predetermined current at a low value to reduce the power consumption of the voltage translator.

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Chandler, AZ, United States of America

Robert P Dixon