National Semiconductor Corporation

Robert Oppen

Steven Michael Barrow

Steven L Harris

Robert Bell

A minimum frequency synchronization discriminator for use in providing a clock signal for a switch mode power supply automatically detects when the frequency of a sync signal is above a minimum frequency and causes the sync signal to serve as the clock signal for the controller. If the frequency of the sync signal is below the minimum frequency, the minimum synchronization frequency discriminator causes the output signal of the internal oscillator to serve as the clock signal.

Minimum synchronization frequency discriminator

Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMOS comparator that includes a built-in offset. The first and second comparators can be arranged such that the built-in offset of the first comparator dominates the overall operation at the start of the control pulse. The start of the PWM control pulse is initiated by a ramp voltage and a predetermined reference level instead of a clock edge. The PWM control pulse can be linearly varied down to a zero pulse width. The PWM control pulse may be used to control the on-time of the switching element in a switching-type converter.

Two comparator voltage mode PWM

The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.

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Chandler, AZ, United States of America

Robert Oppen