Xilinx, Inc.

Research Triangle Institute

Transmute, Inc.

Sixis, Inc.

Robert O Conn

Kameswara K Rao

Tim Tuan

Robert W Wells

Robert D Patrie

Kim L Hailey

Stephen M Trimberger

Austin H Lesea

Steven J Carey

Christopher H Kingsley

Khue Duong

Daniel Y Chung

Steven P Young

Charles R Erickson

Mark A Alexander

David L Ferguson

Lois D Cartier

Gil A Speyer

Daniel S Stevenson

Bernard J New

Michael J Hart

Peter H Alfke

Neil G Jacobson

Kevin T Look

Gary R Lawman

Siuki Chan

John E Mahoney

David F Myers

Matthew T Murphy

Edel M Young

Jan L deJong

William H Pabst

An accelerator assembly includes a first chip and a second chip. An acceleration channel is formed into a surface of a first side of the first chip. The first side of the first chip is covalently bonded to a first side of the second chip such that the channel is a tubular void between the first and second chips. The channel has a tubular inside sidewall surface, substantially no portion of which is a metal surface. The channel has length-to-width ratio greater than five, and a channel width less than one micron. There are many substantially identical channels that extend in parallel between the first and second chips. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

Accelerator having acceleration channels formed between covalently bonded chips

Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.

In system reflow of low temperature eutectic bond balls

An ion accelerator includes a plasma ion source and a micro-collimator. The micro-collimator has a plurality of channels. The length-to-width ratio of each channel is greater than five, and the channel width is less than one micron. The ion source is coupled to the micro-collimator such that ions from the ion source pass into the channels, and then through the plurality of channels. In one specific example, the ion source produces cold ions that have only a small amount of lateral momentum. Each channel is an individually gated acceleration channel that is formed into a solid dielectric material. Ions are accelerated down the acceleration channel. The ion accelerator forms a part of an ionjet head of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

Accelerator having a multi-channel micro-collimator

An accelerator assembly includes an acceleration channel that passes in a straight line through a plurality of accelerator cells. Each cell includes an acceleration region and a drift region. The drift region includes a high voltage plate and a grid electrode, where the grid electrode is disposed between the high voltage plate and the channel. In each cell, a large DC voltage is present on the high voltage plate. A voltage on the grid electrode is controlled such that at a first time an ion in the channel is attracted toward the high voltage plate, and such that at a second time the ion is shielded and is not attracted toward the high voltage plate. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system that can direct write an image onto a 300 mm diameter wafer in one minute.

Accelerator on a chip having a grid and plate cell

An assembly includes a cold ion source and a chip. The cold ion source is fixed to the chip so that ions from the ion source can enter an acceleration channel in the chip. In one specific example, the ion source includes an ion exchange membrane that produces cold ions in that the ions as produced have an energy of less than 30 eV. The chip includes a substrate (such as a semiconductor substrate or a glass substrate) and a dielectric layer disposed on substrate, where the acceleration channel is a channel formed into the dielectric layer. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.

Accelerator on a chip having a cold ion source

A TSV structure suitable for high speed signal transmission includes a metal strip portion that extends through a long and small diameter hole in a substrate. In one example, the metal strip portion is formed by laser ablating away portions of a metal sheath that lines a cylindrical sidewall of the hole, thereby leaving a longitudinal section of metal that is the metal strip portion. A second metal strip portion, that extends in a direction perpendicular to the hole axis, is contiguous with the metal strip portion that extends through the hole such that the two metal strip portions together form a single metal strip. Throughout its length, the single metal strip has a uniform width and thickness and therefore can have a controlled and uniform impedance. In some embodiments, multiple metal strips pass through the same TSV hole. In some embodiments, the structure is a coaxial TSV.

Through-substrate via having a strip-shaped through-hole signal conductor

An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.

Preventing breakage of long metal signal conductors on semiconductor substrates

A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

Integrated semiconductor substrate structure using incompatible processes

A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.

Integral metal structure with conductive post portions

A method of operating an integrated circuit ('IC') is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

Disabling unused/inactive resources in an integrated circuit for static power reduction

A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Interposer for redistributing signals

An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.

Large substrate structural vias

An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigapascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.

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Los Gatos, CA, United States of America

Robert O Conn