Micron Technology Incorporated

Facebook Technologies, LLC

Meta Platforms Technologies, LLC

Robert Nasry Hasbun

Dean D Gans

Timothy Mowry Hollis

Jeffrey P Wright

Sharookh Daruwalla

Nadav Grossinger

Nitay Romano

Niv Kantor

Ricardo Garcia

Daniele Balluchi

Michael Anthony Hall

Zihe Gao

Jonatan Ginzburg

Michael Hall

Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

Time delay indication for host in memory system

Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Communicating data with stacked memory dies

An audio system in a local area providing an audio signal to a headset of a remote user is presented herein. The audio system identifies sounds from a human sound source in the local area, based in part on sounds detected within the local area. The audio system generates an audio signal for presentation to a remote user within a virtual representation of the local area based in part on a location of the remote user within the virtual representation of the local area relative to a virtual representation of the human sound source within the virtual representation of the local area. The audio system provides the audio signal to a headset of the remote user, wherein the headset presents the audio signal as part of the virtual representation of the local area to the remote user.

Spatial audio and avatar control at headset using audio signals

Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Variable modulation scheme for memory device access or operation

A depth camera assembly (DCA) determines depth information for a local area. The DCA includes a camera assembly and at least one illuminator. The DCA may select a subset of the VCSELs to provide illumination at any given time. The illuminator may comprise near-field VCSELs configured to generate a structured light (SL) pattern for depth sensing in the near-field and far-field VCSELs configured to generate a SL pattern for depth sensing in the far-field. The near-field VCSELs may comprise a linear emission region which is shorter than a linear emission region of the far-field VCSELs. The DCA may generate and phase shift a quasi-sinusoidal SL pattern. The DCA may phase shift the quasi-sinusoidal SL pattern by alternating which traces on the illuminator are active.

VCSEL arrays for generation of linear structured light features

In one embodiment, a system includes at least one projector configured to project a plurality of projected patterns, where a projected lighting characteristic of each of the projected patterns varies over a time period in accordance with an associated predetermined temporal lighting-characteristic pattern, a camera configured to capture images of detected patterns during the time period, and one or more processors configured to: determine, for each detected pattern, a detected temporal lighting-characteristic pattern based on variations in a detected lighting characteristic of the detected pattern, identify a detected pattern that corresponds to one of the projected patterns by comparing at least one of the detected temporal lighting-characteristic patterns to at least one of the temporal lighting-characteristic patterns, and compute a depth associated with the detected patterns based on the one or more of the projected patterns, the detected pattern, and a relative position between the camera and the projector.

Depth sensing using temporal coding

Indication in memory system or sub-system of latency associated with performing an access command

Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.

Prefetch management for memory

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

Multiple concurrent modulation schemes in a memory system

Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

Prefetch signaling in memory system or subsystem

Systems, devices, and methods related to non-volatile memory are described. A non-volatile memory array may be employed as a main memory array for a system on a chip (SoC) or processor. A controller may interface between the non-volatile memory array and the SoC or processor using a protocol agnostic to characteristics of non-volatile memory operation including different page sizes or access time requirements, etc. A virtual memory bank at the controller may be employed to facilitate operations between the SoC or processor and the non-volatile memory array. The controller may be coupled with a buffer to facilitate rapid data operation, and the controller may be configured to selectively access data at the non-volatile array to account for data stored in the virtual memory bank or the buffer. The controller, the virtual memory bank, and the buffer may be configured on one chip separate from the SoC or processor.

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San Jose, CA, United States of America

Robert Nasry Hasbun