Texas Instruments Corporation

Other

Texas Instruments Incorportated

Robert N Rountree

Charvaka Duvvury

Darryl Gene Walker

Francis Hii

David W Bergman

Dan Cline

Tatsuroh Maki

Allan T Mitchell

Troy H Herndon

Harvey J Stiegler

Jeremy Abel Ganz

Barbara P Rountree

An apparatus to facilitate weight lifting exercises is disclosed. The apparatus includes a palm plate having a hook portion configured to receive a weight bar. A detent is rotationally connected to the palm plate and configured to constrain the weight bar within the hook member in a closed position. An optional thumb lever may be connected to the detent to facilitate opening and closing the detent.

Weight glove clamp

A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal () and a second terminal (). A first lightly doped region () having a first conductivity type (N&#x2212;) is formed on a second lightly doped region () having a second conductivity type (P&#x2212;). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region () having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region. A first transistor () having a control terminal and having a first current path terminal coupled to the third heavily doped region and a second current path terminal coupled to the second terminal is arranged to control a holding voltage of the circuit.

Programmable SCR for ESD protection

A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal () and a second terminal (). A first lightly doped region () having a first conductivity type (N&#x2212;) is formed on a second lightly doped region () having a second conductivity type (P&#x2212;). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region () having the second conductivity type (P+) is formed at least partially within the first lightly doped region at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region.

A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit () is coupled to the semiconductor controlled rectifier.

Low voltage efuse programming circuit and method

A method of protecting a power supply voltage in an integrated circuit is disclosed. The method includes storing charge in a charge reservoir capacitor (), receiving a power supply sample voltage (), and receiving a load power supply voltage (VDDL,). The power supply sample voltage is compared to the load power supply voltage (). Charge is added from the charge reservoir capacitor () to the load power supply (VDDL) through transistorand capacitorin response to the step of comparing.

Power supply protection circuit and method

A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier () having a signal bit line () extending in a first direction and having a memory cell () suitable for a read operation. A second sense amplifier () has a second bit line () adjacent and parallel to the signal bit line. The second bit line receives a precharge voltage during the read operation. A third sense amplifier () has a third bit line () adjacent and parallel to the signal bit line. The third bit line receives the precharge voltage during the read operation.

Low noise memory array

A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier () having a first bit line () extending in a first direction and a second bit line () extending in a second direction parallel to the first bit line. A second sense amplifier () has a third bit line () adjacent and parallel to the first bit line. The third bit line remains inactive while the first bit line is active.

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS.and) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch () coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider () is coupled in series with the switch. A sense transistor () has a sense control terminal () and a current path coupled between an output terminal () and a reference terminal (). A first capacitor () has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor () has a control terminal coupled to receive a read signal (), and a current path coupled between the output terminal and a bit line ().

Low power, single poly EEPROM cell with voltage divider

A weed extractor is designed with a shaft (100) having a handle end and a distal end. A foot piece (116) has a first end and a second end. The first end is slidely attached to the shaft proximal to the distal end. The foot piece extends laterally from the shaft. A bit assembly (118) has a plurality of pivotally mounted opposed spikes. The bit assembly has an open position and a closed position, and moves between the open position and the closed position in response to movement of the foot piece with respect to the shaft. At least two opposed spikes are spaced apart from a plane bisecting an angle between the at least two opposed spikes in the open position. A part of each of the at least two opposed spikes intersects the plane in the closed position.

Weed extractor

An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.

Depletion controlled isolation stage

A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.

Row decoder with level translator

A low capacitance bus driver circuit includes, in this example, P-channel and N-channel output transistors with input gates connected by means of CMOS pass gates to a common input terminal and having respective P-channel and N-channel transistors connected to the input gates of the output transistors so as to place them in a high impedance state when the CMOS pass gates are disabled. Input capacitance of the bus driver circuit is greatly reduced by elimination of CMOS gate capacitance when the bus driver is enabled. When the bus driver is not enabled, it provides optimal performance of a single gate delay from input to output without the need for series connected output devices or correspondingly higher input capacitance.

Low capacitance bus driver

A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.

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Plano, TX, United States of America

Robert N Rountree