Motorola Corporation

Semiconductor Components Industries, LLC

Robert N Dotson

Robert Bruce Davies

Ira G Miller

Robert L Vyne

Michael W Null

Richard S Griffith

Thomas D Petty

William F Davis

Gary W Hoshizaki

Robert B Davis

An integrated circuit ( ) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit ( ) when its temperature exceeds a predefined value. First and second current sources ( ) respectively produce first and second reference currents (I , I ) representative of first and second die temperatures of the integrated circuit. A current mirror ( ) has an input ( ) for summing the first and second reference currents and an output ( ) for providing a mirror current (I ). A detection circuit ( ) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (V ) as a function of the first and second die temperatures.

Thermal shutdown circuit with hysteresis and method of using

Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0.degree. to 70.degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current. An output stage provides approximately fifty milliamps of current drive and is quiescent until the output driver is selected.

Low voltage operational amplifier input stage and method

A trim circuit (10) and method of reducing offset voltages in a differential input stage. The differential input transistors (32 and 42) have separate bulk terminals for receiving a voltage to compensate for the input offset voltage. A current source (60) supplies a static current to the offset compensation circuit for generating a bias voltage at node (55). The transistors (64 and 66) receive a voltage at input terminals (30 and 40) and supply an additional current to an offset compensation circuit (20). A switch circuit (50) has switch pairs (52, 56, and 54, 58) for transferring a voltage to the bulk terminal of one of the differential transistors (32 and 42) while grounding the bulk terminal of the other transistor. The differential voltage supplied across the bulk terminals of transistors (32 and 42) changes the threshold voltage of the transistors reducing the offset voltage of the input stage.

Method and circuit for reducing offset voltages for a differential input

Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0.degree. to 70.degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current.

Low voltage operational amplifier and method

A memory cell sense technique for sensing a logic state of a memory cell. An output level translator (33) which can be preset to a predetermined logic state is utilized. A current source circuit (24) and a current sink circuit (26) change memory cell sensing into two distinct modes. In the first mode, the memory cell logic state is identical to the preset output logic state. The memory cell generates a differential voltage which is countered by a differential voltage created by the current source and current sink circuit. Inputs to a sensing circuit common mode and non-complemented output (44) remains in the preset logic state. In the second mode, the current source circuit and current sink circuit aid the memory cell in generating a differential voltage. The sensing circuit senses the differential voltage and changes the non-complemented output (44) from the preset logic state.

Memory cell sense technique

A propagation delay generator is provided for controlling the duration of a bubble generate waveform of a bubble memory system. A first means is responsive to a digital input signal and provides an initializing signal to a current source. A capacitor is charged, responsive to an R-C time constant, by an increased voltage level prompted by the initializing signal. A second means is responsive to the charging signal in excess of that required to charge the capacitor. The second means thereby provides a digital output that is delayed from the digital input signal.

Propagation delay generator

In a voltage boost circuit for use in conjunction with a bubble memory operational driver, an output transistor is alternately turned on and off. When turned on, current flows through an inductor. When turned off, a high voltage is built up across the inductor which causes charge to be transferred to and stored in a capacitor. When the output transistor is turned on so as to permit current to flow through the inductor, a .DELTA.V.sub.BE /R current representative of the current flowing through the output transistor is compared with a .DELTA.V.sub.BE /R reference current. When the first current reaches and exceeds the reference current, the output transistor is turned off.

Current sense circuit for a bubble memory voltage booster

A current ramp generator is provided for controlling the fall time of a bubble generate waveform of a bubble memory system. Gate circuitry is responsive to a digital input signal and provides an initializing signal to a current source. The current source charges a capacitor and thereby provides an increasing signal to a current mirror whose output sinks current from a control amplifier of the bubble memory system.

Current ramp generator

A current amplifier is provided having a single control amplifier and a plurality of output stages. The desired output stage is digitally selected. The ratios of the output stage currents may be selected during the metalization process. A single capacitor compensates for all output stages regardless of which output stage is selected.

Current amplifier having multiple selectable outputs

A pulse stretching integrated circuit includes an on-chip capacitor. A first transistor means including an input transistor and an emitter follower transistor supplies a charging current to the capacitor so as to charge it to a first voltage when an input signal pulse is in a first logical state. A differential transistor pair has a first input coupled to the emitter follower transistor and to the capacitor and has a second input coupled to a reference voltage for generating a first output when the capacitor voltage is less than the reference voltage and for generating a second output when the capacitive voltage is greater than the reference voltage. An additional transistor is coupled to the capacitor for discharging the capacitor when the input signal pulse is in a second logical state causing the voltage at the first input of the differential pair to fall below the reference voltage.

Pulse stretching and level shifting circuit

A sense amplifier which is fully integrated has an on-chip voltage regulator to provide essentially error free operation. The sense amplifier provides peak-to-peak signal detection for comparison to a threshold voltage by a comparator. The output of the comparator is coupled to an RS flip-flop. The output of the RS flip-flop is coupled to a D flip-flop. The use of an RS flip-flop as well as a D flip-flop eliminates clocking problems caused by skewing and keeps a stored detected signal from changing prematurely.

Bubble memory sense amplifier

A current amplifier uses a current mirror arrangement as an operational amplifier whose output has limited swing. The limited swing is achieved through a plurality of series connected diodes connected to a control input of the amplifier and to the output of the operational amplifier. The control input is coupled through a transistor to inhibit the output of the current mirror arrangement. The output node is coupled to an output for the current amplifier through a Darlington arrangement which provides high current gain.

Current amplifier

A circuit for providing the gate of a bubble memory with a precision current pulse at a high voltage is manufactured using a low voltage process; i.e. BV.sub.ceo is approximately 18 volts. In order to accomplish this, first and second voltage level shifting stages are cascoded and the output transistors thereof are used as Zener level shifters each level shifting downward by a BV.sub.ceo when only a small voltage is dropped across the load. If the voltage drop across the load increases, the cascoded output transistors may enter their active region and are prevented from going into saturation by saturation clamps so as to not introduce unwanted delays in the rise or fall times of the current pulse.

High voltage bubble memory pulse generator output stage

In a voltage boost circuit for use in conjunction with a bubble memory operational driver, an output transistor alternately turns on and off so as to permit current to flow through an inductor which, when terminated by turning off the output transistor, causes a high voltage to be built up across the inductor which causes charge to be transferred to and stored in a capacitor. The output transistor is not turned on again until the voltage across the inductor falls below a predetermined value. A current mirror circuit is coupled to the comparator input and includes a buffer transistor which, when the voltage at the comparator input exceeds the break-down voltage of the buffer transistor, acts as a BV.sub.ceo level shifter.

Voltage sense circuit for a bubble memory voltage booster

A current limiting circuit is provided wherein the monitored voltage is applied to the base of first and second transistors, the first transistor having a substantially larger emitter area than the second transistor. Impedance means are connected to the emitters of the first and second transistors such that they function in conjunction with the emitter area ratio causing the current flowing through the first transistor to be higher than that flowing through the second transistor at low base voltages, while at higher base voltages the current flowing through the second transistor is higher than flowing through the first transistor. At some intermediate voltage the current flowing through both the first and second transistors is equal. This property may be used, for example, in a voltage regulator so as to divert base drive current from the output transistor at the point where the first and second currents are equal.

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Mesa, AZ, United States of America

Robert N Dotson