Altera Corporation

Robert N Bielby

Krishna Rangasayee

Kerry S Veenstra

Richard G Cliff

Brad Ishihara

A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Apparatus and method for routing of signals

Apparatus and method for low power routing of signals in a low voltage differential signaling system

Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system

The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Programmable voltage regulator

A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.

Memory cells configurable as CAM or RAM in programmable logic devices

Method and apparatus for programmably providing a power supply voltage to an integrated circuit

A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to circuit nodes that are sensitive to noisy environments. The programmable threshold-triggered buffers are connected to circuit nodes that have critical timing requirements.

Programmable logic device with selectable schmitt-triggered and

A programmable logic device architecture incorporating a cross-bar switch is disclosed. In a preferred embodiment, a plurality of logic cells is programmably interconnected to form an array of logic cells capable of implementing complex logic functions. A user selectable cross-bar switch block having dedicated programmable connectors is coupled to the array of logic cells by way of a mode control circuit switch. The mode control circuit switch is arranged to couple the dedicated cross-bar switch block to the array of logic cells in a first mode and to de-couple the cross-bar switch block from the array of logic blocks in a second mode.

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Pleasanton, CA, United States of America

Robert N Bielby