Motorola Corporation

Robert N Allgood

Richard W Ulmer

Stephen H Kelley

Henry Wurzburg

Joe W Peterson

Roger A Whatley

James A Miller

Kevin K Luke

A voltage detecting circuit is provided for generating an output signal when an input signal exceeds the power supply voltage by a predetermined amount. A reference current is established by an output stage using a first current mirror. A second current mirror is connected to the output stage and detects the input voltage level by forcing a greater or lesser amount of current through the output stage to provide a high or low level output voltage.

High voltage detection circuit

An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

MOS Analog switch driven by complementary, minimally skewed clock signals

A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.

Circuit for interfacing with both TTL and CMOS voltage levels

An input buffer circuit for translating TTL level inputs to CMOS levels and which constitutes a part of a monolithic semiconductor device is provided. An input inverter stage has the source of its load transistor connected via a bipolar transistor to a first voltage level. When a second voltage level at which the monolithic semiconductor device is intended to operate exceeds the first voltage level, an MOS transistor coupled in parallel with the bipolar transistor bypasses the bipolar transistor and connects the source of the load transistor directly to the first voltage level, thus eliminating the V.sub.BE drop of the bipolar transistor. The bypass means compensate for the body effect of the load transistor and maintain the switch point of the input inverter stage at a relatively constant point.

Input buffer

An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A-and Mu-255 law PCM conversion capability. Coupled directly to the C DAC is an operational amplifier receive filter circuit which utilizes the C DAC as an input capacitor thereby eliminating the need for a buffer amplifier and allowing the DAC to be used for both analog to digital and digital to analog conversion.

Digital to analog converter

Multiple function operational amplifier circuit

There is provided a reverse battery protection circuit which does not have current limiting resistors to limit current in all portions of the circuit. The protection is obtained by connecting the substrate tubs of N-channel drivers through another N-channel transistor to VSS. The another N-channel transistor has its gate electrode connected to voltage terminal VDD. Accordingly, when reverse voltage is applied to the circuit, VDD will be negative and therefore the another N-channel transistor will not be conductive. This prevents the output driver transistor from becoming a conductive parasitic bipolar transistor.

Reverse battery protection

An MOS oscillator is provided which has reduced sensitivity to power supply voltage variations and to threshold processing variations. A plurality of field effect transistors are connected in series to provide reference voltages to establish two trip points for a comparator. A second input of the comparator is connected to a capacitor whose charging and discharging is controlled by the output of the comparator. The plurality of series connected transistors form unsymmetrical active device dividers. The unsymmetrical configuration is chosen such that power supply variations and threshold variations cancel much of the charge current variation due to these variations. Matched current sources are used throughout the oscillator circuit.

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Austin, TX, United States of America

Robert N Allgood