Amazon Technologies, Inc.

Robert Michael Johnson

Asif Khan

Mark Bradley Davis

Nafea Bshara

Christopher Joseph Pettey

Islam Mohamed Hatem Abdulfattah Mohamed Atta

Erez Izenberg

Thomas A Volpe

Marc John Brooker

Marc Stephen Olson

Kypros Constantinides

Islam Atta

Norbert Paul Kusters

Anthony Nicholas Liguori

Matthew Shawn Wilson

Kiran Kalkunte Seshadri

Timothy David Gasser

Vithal Dattatraya Shirodkar

Nobert Paul Kusters

Stanislav Spassov

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Configurable logic platform

Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

Networked programmable logic service provider

Programmatically defined fields of metadata for a network packet may be generated. Instructions indicating different portions of data from different headers of a network packet may be stored at a packet processor. When a network packet is received, the different portions of the data may be extracted from the different headers of the packet according to the instructions and provided to other stages of the packet processor for processing. Different portions of the same programmatically defined field may be utilized at different stages in the packet processor. The programmatically defined field may be used to generate a hash value that selects an entry in a lookup table describing a forwarding decision for a network packet.

Generating programmatically defined fields of metadata for network packets

Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating signature information with the client configurable logic for various purposes.

Client configurable hardware logic and corresponding signature

Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Controlling access to previously-stored logic in a reconfigurable logic device

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Configurable logic platform with multiple reconfigurable regions

Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating clock information with the client configurable logic for various purposes.

Client configurable hardware logic and corresponding hardware clock metadata

Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.

Interception of identifier indicative of client configurable hardware logic and configuration data

Server computers often include one or more input/output (I/O) devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O device. For example, host memory descriptors can be stored in a memory of the I/O device to facilitate placement of the requested data.

Ingress data placement

Access control is provided for peer-to-peer communication between a source peripheral device and a destination peripheral device without going through a host device. The access control mechanism can allow or block a request for a transaction to go out via a port of the source peripheral device to the destination peripheral device by comparing an attribute associated with the transaction with a filter attribute stored in memory. Embodiments of the disclosed technologies can allow programming of different filter attributes for different tenants in a multi-tenant environment.

Growing community of inventors

Austin, TX, United States of America

Robert Michael Johnson