Marvell Asia Pte., Ltd.

Robert Michael Bunce

Nir Ofir

A memory array includes a plurality of memory devices, each of which includes a memory configured to store packet data and a request arbiter configured to interface with other memory devices of the memory array. The request arbiter filters invalid requests from a plurality of requestors, and determines a bitvector representing a sequence of the plurality of requestors, the bitvector indicating whether each of the plurality of requestors has a valid request. The request arbiter outputs an indication of a first request to be serviced by the memory device, and shifts the bitvector to determine a second request to be serviced by the memory device.

Single cycle request arbiter

A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.

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Cary, NC, United States of America

Robert Michael Bunce