Imagination Technologies Limited

Robert McKemey

Max Freiburghaus

Sam Elliott

Thomas Michael Rose

Emiliano Morini

A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by The hardware logic comprises a plurality of multipliers and adders arranged to implement a m-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Iterative estimation hardware

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kdifference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Verification of hardware design for integrated circuit implementing polynomial input variable function

Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs. The relevant portion of the output data of the hardware design is verified as the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

Verifying a hardware design for a multi-stage component

A method of selecting, in hardware logic, an ilargest or a psmallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the riteration, the method comprises: summing an (m&#x2212;r)bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rbit of the selected number is determined and output and additionally the (m&#x2212;r&#x2212;1)bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m&#x2212;r)bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Selecting an ith largest or a pth smallest number from a set of n m-bit numbers

Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals. The method comprises: for each stage of the plurality of stages from the second stage to the last stage: (a) verifying that a relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs; and (b) verifying that the relevant portion of the output data of an instantiation of the hardware design is the same if the instantiation is in the same state (i) when that stage is enabled in a cycle and any subsequent stages are enabled in subsequent cycles by a second minimal sequence of inputs and (ii) when that stage is stalled, then that stage is enabled in the next cycle and the subsequent stages are enabled in subsequent cycles by the second minimal sequence of inputs.

Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

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Hemel Hempstead, United Kingdom

Robert McKemey