Psemi Corporation

Peregrine Semiconductor Corporation

Murata Manufacturing Co., Ltd.

Robert Mark Englekirk

Tero Tapio Ranta

Keith Bargroff

Christopher C Murphy

Simon Edward Willard

Tae Youn Kim

Christopher Nelles Brindle

Shawn Bawell

Robert W Greene

Poojan Wagh

David Kovac

Eric S Shapiro

Kashish Pal

Jonathan James Klaren

Dylan J Kelly

Dan William Nobbe

Ronald Eugene Reedy

Emre Ayranci

Keith J Rampmeier

Tsuyoshi Takagi

Ikumi Tokuda

Neil Calanca

Arpita Moghe Chadha

Circuits and methods for defining functionality of swappable pins are provided. A power-on-reset (POR) circuit detects that a supply voltage is above a POR threshold during start-up or a reset operation. Transmission gate circuits monitor inputs from a first pin and the second pin and deactivate once the POR circuit detects that the supply voltage is above the POR threshold. A latch circuit receives outputs of the transmission gate circuits as inputs. Once the supply voltage is above the POR threshold, the latch circuit generates a first output corresponding to the first pin, and a second output corresponding to the second pin, where the first pin is defined as a I/O pin and the second pin is defined as a capacitance pin or vice versa based on the first output and the second output.

Pin determination for single-conductor interface systems and methods

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Methods and devices to detect defects in gate oxides of MOSFETs are disclosed. The disclosed methods and devices rely upon current measurements or decay measurements of the voltages across MOS capacitors. The described devices can be implemented in the RF circuits with elements having stringent reliability requirements.

Current measurement for defect detection

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same Vas during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same Vas during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a 'trickle current' state) that keeps both Vand Vclose to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

Transient stabilized SOI FETs

Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage Vand a fuse voltage V, and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (V) than V. Since Vmay be about 0.1V, that turn-ON voltage may be as low as about 0.1V+V, and thus would be less than a Vof about 1V.

Low-voltage fuse read circuit

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a 'controllable' resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

Controllable temperature coefficient bias circuit

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Cascode amplifier bias circuits

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Gate drivers for stacked transistor amplifiers

An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

Low-noise high efficiency bias generation circuits and method

Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments preform the following functions: detecting the initial phase of device startup; determining which of pins A and B is coupled to an I/O line (and thus is the I/O pin), and which is coupled to the storage capacitor (and thus is the CAP pin); and generating a flag signal indicating that determination to other circuitry within the peripheral. Detection of pin characteristics is determined at device startup by latching the fastest rising signal on pins A and B, flagging that signal line as being the I/O line, and preventing further changes to the latch output until the next startup cycle.

PIN determination for single-conductor interface

Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain 'droop' due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

Power amplifier self-heating compensation circuit

An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Tuning capacitance to enhance fet stack voltage withstand

Charge pump circuits having a fractional negative voltage output from a positive voltage input. A control circuit provides for feedback control of the output of such a charge pump, and may include dynamic adjustment of the charge pump output based on one or more factors. In some embodiments, two or more charge pumps are coupled in a differential configuration such that while one set of capacitors are in series charging, at least one other set of capacitors is discharging. One embodiment encompasses a fractional negative voltage charge pump including n≥2 capacitors configured to be coupled in series between an input voltage and ground during a charging phase, and in parallel between ground and an output terminal during a discharging phase. The fractional negative voltage charge pump outputs a negative voltage that is no more than 1/n of a positive voltage input in magnitude.

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Littleton, CO, United States of America

Robert Mark Englekirk