Cadence Design Systems, Inc.

Robert MacDonald

Jalal Wehbeh

Harsh Vardhan

Ajish Thomas

Aswin Ramakrishnan

Federico Politi

A method for simulating an integrated circuit model is provided. The method includes receiving partition netlists of an integrated circuit in a partition scheduler and scheduling, by at least one computer, an execution of a computational thread associated with a first partition netlist. The method also includes preparing input data for a task and storing the input data set in an object storage. Also, the method includes executing, by the computer, the task in the computational thread. The method also includes building dependency trees between multiple tasks for reducing the input/output data overhead, and caching information that may be necessary for each task but may be reusable by the task when such information is unavailable from previously computed tasks.

Reduced overhead for massive parallel processing

A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components. When a second input stimulus vector is associated with a second delay arc that is equivalent to the first delay arc in the logic path, the method includes selecting one of the first or second input stimulus vectors for a set of input stimuli vectors. The method further includes determining an electromigration effect on the partition netlist with the input stimuli vectors.

Exhaustive input vector stimuli for signal electromigration analysis

A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of vectors for nodes electrically connected to the local output node. Each CCC's component characteristic function is expanded to form a local characteristic function relative to one or more other upstream CCC. Each local characteristic function is thereby formed exclusive of any upstream local output node electrically disconnected from its local output node. At least one feasible vector is selectively generated from the local characteristic functions according to requirements predefined for a parametric measurement.

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Austin, TX, United States of America

Robert MacDonald