Mitsubishi Semiconductor America, Inc.

Mitsubishi Electric and Electronics U.s.a., Inc.

Robert M Walker

Stephen Michael Camacho

Tim Lao

George William Alexander

Rhonda Cassada

A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

Self-adjusting clock phase controlled architecture

A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.

System and method for column access in random access memories

A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.

Addressing system in a multi-port RAM having main and cache memories

One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Voltage pump for integrated circuit and operating method thereof

An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

Driving memory bitlines using boosted voltage

An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.

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Rougemont, NC, United States of America

Robert M Walker