Intel Corporation

Nvidia Corporation

Robert M Toth

Tomas G Akenine-Moller

Jon N Hasselgren

Carl Jacob Munkberg

Franz Petrik Clarberg

Magnus Andersson

Bjorn Johnsson

Tomas Guy Akenine-Möller

Marco Salvi

Jim K Nilsson

Karthik Vaidyanathan

Prasoonkumar Surti

Subramaniam M Maiyuran

Michael Apodaca

Ingo Wald

Brent E Insko

Tomasz Janczak

Kalyan Kumar Bhiravabhatla

Aditya S Yanamandra

Larry D Seiler

Aaron Eliot Lefohn

Jacob J Munkberg

Tim Foley

Jim Kjell David Nilsson

Matt Pharr

Tomas G Akenine-MÖLLER

In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

Decoupled shading pipeline

An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.

Apparatus and method for non-uniform frame buffer rasterization

An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.

Replicating primitives across multiple viewports

A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.

Virtual reality/augmented reality apparatus and method

A texture level of detail (LOD) approximation may be performed utilizing ray differentials and a G-buffer. For example, a scene to be rendered is identified, and a G-buffer of the scene is rendered. Additionally, ray tracing is started for the scene, and during the ray tracing, a ray differential is created by accessing the G-buffer. Further, the created ray differential is appended to a current ray, and the created ray differential is traced.

Creating a ray differential by accessing a G-buffer

Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.

Hierarchical Z-culling (HiZ) optimization for texture-dependent discard operations

In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Reducing power consumption during graphics rendering

A method, computer readable medium, and system are disclosed for performing a texture level-of-detail approximation. The method includes the steps of identifying a scene to be rendered, projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene, determining a footprint angle of the pixel, determining a curvature measure for the geometry element at the first hit point within the scene, computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element, and performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.

Performing a texture level-of-detail approximation

Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.

Minimum/maximum and bitwise and/or based coarse stencil test

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Lund, Sweden

Robert M Toth