International Business Machines Corporation

Robert M Quinn

Paul E Bakeman, Jr

Arup Bhattacharyya

Henry J Geipel, Jr

Michael L Kerbaugh

Jeffrey A Robinson

Jeffrey P Kasold

Andres G Fortino

Richard Alan Unis

William John Schuele

Spacers are formed having widths that vary as a function of the spacing between the mandrels upon which the conformal material that defines the spacers is deposited and etched. As the spacing between adjacent mandrels decreases, the width of the resulting spacers decreases. The correlation between mandrel spacing and sidewall structure width is independent of the thickness of the conformal material as-deposited. As the spacing between the mandrels decreases, the decrease in width becomes more pronounced, particularly at mandrel spacings of five microns or less. Thus, by making adjacent mandrels closer together or further apart and adjusting mandrel height, active/passive components having differing widths/lengths may be formed from the same conformal layer.

Formation of variable-width sidewall structures

A method for reducing the susceptibility of integrated circuit dynamic memory devices to environmentally produced radiation, such as alpha particles, in which a buried layer, having a majority carrier concentration substantially equal to or greater than the concentration of free carriers generated by the radiation and being between one and four orders of magnitude greater concentration than that of the semiconductor substrate, is ion implanted within a few microns of the substrate surface after at least one major high temperature processing step in the manufacturing process has been completed.

Method for increasing the radiation resistance of charge storage

A method of providing less than one micron p-n junction regions for IGFET devices in which a high concentration of arsenic is implanted so that its peak lies near the surface of a semiconductor substrate. Phosphorus is also implanted with an energy to provide a maximum concentration below that of the arsenic and of a magnitude at least one order of magnitude less than that of arsenic. An oxidation/anneal step thermally diffuses the implanted ions to form a junction less than one micron in thickness.

Method for forming IGFET devices having improved drain voltage

Disclosed is a method in the manufacture of FET single device memory cells and arrays for controlling a doped oxide diffusion profile and thereby controlling substrate diffusion and doped oxide diffusion source overlap and controlling the inherent formation of parasitic capacitance. This is accomplished by controlling the variation of four interrelated essential parameters in the production of a single device memory cell array with the consequent result of minimizing said parasitic capacitance encountered in certain overlap conditions and thereby maintaining and increasing device performance. Process conditions which are controlled relative to one another are the thickness of the doped oxide on a monocrystalline semiconductor silicon substrate, the amount of over etch carried out in the formation of a diffusion source island, the thickness of oxide formed on unprotected substrate areas during diffusion drive-in, and the depth of a particular diffusion into the substrate, known as X.sub.j.

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South Burlington, VT, United States of America

Robert M Quinn