International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Robert M Piper

Pravin S Patel

David Thomas Windell

James Edward Hughes

Christopher Collier West

Timothy Schlude

Thomas Francis Lewis

Michael Leo Scollard

Henry Gaines McMillan

Daniel Barus

Robert Joseph Evans

Kamran Amini

Paul Maylon Smith

Donald G Polak

Pivithuru S Perera

Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface configured to communicatively connect to a computing device. The system may also include a multi-channel interface configured to communicatively connect to multiple subrate channels. Further, the system may include a controller configured to communicatively connect the subrate channels with the computing device via the USB interface. The controller may also be configured to communicate, to the computing device, connection specifications for the subrate channels.

Multi-channel universal serial bus (USB) to subrate channel systems

Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Server network diagnostic system

Administering computer processor execution of BIOS code that includes a primary BIOS code and a recovery BIOS code stored in ROM, the ROM operatively coupled to a control module and the processor, where administering processor execution of the BIOS code includes determining, by the control module, a size of the ROM; generating, by the control module in dependence upon the size of the ROM, an address for the primary BIOS code and an address for the recovery BIOS code; starting, by the control module, operation of the processor for execution of the primary BIOS code including providing, to the processor, the address for the primary BIOS code; and if executing the primary BIOS code fails, restarting, by the control module, operation of the processor for execution of the recovery BIOS code including providing, to the processor, the address for the recovery BIOS code to the processor.

Generating a primary BIOS code memory address and a recovery BIOS code memory address, where the recovery BIOS service code is loaded when the primary BIOS code fails to execute

Methods and systems for implementing such methods for providing server diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. Display of diagnostic service notifications may allow for completion of various service operations associated with service notifications once information specific to a fault is presented. Such service operations may include placing a system in standby mode, transferring workloads to other systems, initiating a firmware update, placing the system in a mode that allows for physical maintenance, or ordering parts associated with one or more faults.

A method of controlling the power-on of a computer system by providing a plurality of monitor lines interconnected with respective components of the computer system, monitoring the lines using a control circuit in response to a power-on reset signal, and executing a system power-on sequence in response to a determination by the control circuit that the components of the computer system are functioning properly. If the computer system has a plurality of CPU slots, the control circuit determines if a CPUs or terminator cartridges is plugged into the CPU slots, and determines that a properly matched CPU has been installed into the system, and that multiple CPUs contain compatible power supply requirements. Finally, the control circuit can determine that a power regulator is functioning properly.

Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality

Growing community of inventors

Apex, NC, United States of America

Robert M Piper