Xilinx, Inc.

Robert M Ondris

Steven P Young

Trevor J Bauer

Brian C Gaide

Parag Upadhyaya

Alireza S Kaviani

Raymond C Pang

Nagaraj Narasimh Savithri

Dinesh D Gaitonde

Alan C Wong

Greg W Starr

John D Logue

Sarosh Azad

Christopher J Borrelli

Tao Pi

Kwansuhk Oh

Shawn K Morrison

Chiao K Hwang

Loren Jones

Seu Wah Low

James J Koning

An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

Generation of delay values for a simulation model of circuit elements in a clock network

An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

Transceiver for providing a clock signal

An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Clock network architecture

Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability ('NBTI') damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.

Preventing transistor damage

A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Circuits and methods of using parallel counter controlled delay lines to generate a clock signal

A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.

Structure for the main oscillator of a counter-controlled delay line

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Santa Clara, CA, United States of America

Robert M Ondris