Cirrus Logic Inc.

Texas Instruments Corporation

S3 Incorporated, Inc.

Other

Hunet Display Technology Inc.

Robert M Nally

John C Schafer

Sudhir Sharma

Christopher L Reinert

Michael E Runas

Frank L Xu

Pete Edward Nelsen

Douglas Michael Berk

Douglas Hamilton

Jeffrey A Niehaus

Donald Richard Tillery, Jr

Kevin Main

Douglas M Hamilton

Masaya Okita

Mark A Fiechtner

A programmable controller having three well-known components used in display controls but put under the control of a programmable 'sub-field ' timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.

TFT display controller

A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station without additional connectors on the portable computer and the docking station.

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A method of providing a low cost quantized nonlinear scaler for a continuous curve includes the steps of providing a quantized coefficient table representing an approximation of the nonlinear continuous curve; applying the table in hardware to locate coefficients in the table, and applying the coefficients to a scaling pipeline to get scaled data. The nonlinear approximation in the table is achieved by following the rules that the sampled data must be consistent, the quantization points must be consistent, the coefficient curve must be symmetric about its centerline, and the quantization values must be selected so that the sum of all coefficients values in the coefficient curve over all the source points for a given resultant point is always equal to a normalization value.

Quantized nonlinear scaler

A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

Virtual frame buffer control system

A system and method for reducing bottlenecks on a computer bus, by offloading specific types of high-bandwidth data from the system bus and passing that data directly to specialized target busses. In the computer system, the system bus, typically a PCI bus, is monitored for addresses corresponding to specific target devices. When these addresses are detected, the corresponding data is diverted from the system bus to the appropriate specialized bus. By doing so, bandwidth across the system bus is reduced, and the specialized data, which may be time-sensitive or real-time audio or video, is passes rapidly to the appropriate processor.

Method and apparatus for data conversion in a computer bus

Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

Display system with interleaved pixel address

A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are efficiently timesharing a global memory storage area. The received data streams are each divided into fixed portions called spans. The invention is operable for sequencing the movement of the time-sliced spans between the processors, adjusting the scheduling of particular ones of the time-sliced spans as a function of either processor availability or maintenance of real-time transmission of the received real-time time-sliced data streams.

System and method for processing multiple received signal sources

A memory system 107,300 is provided which includes a memory 107 having a data area for storing data words and a mask area 302 for storing a control mask. Mask generation circuitry 301 is provided for generating such a control mask for storage in the mask area 302 of the memory 107. Mask controlled memory read control circuitry 303 is provided which is operable to selectively retrieve from the mask area 302 bits of the mask stored therein and in response selectively retrieve and output data words stored in the data area of the memory 107.

Apparatus, systems and methods for controlling data overlay in

A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.

Circuits, systems and methods for modifying data stored in a memory

A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.

Sensing circuitry with boolean logic

Disclosed is a system and method for mixing a plurality of graphics and video signals to create a desired output format, the desired output format being a mixture of the received signals. The mechanisim for achieving this rich format is a multi-modal graphics video overlay controller. The controller having a set of opcodes, selects a subset of the opcode set, this selection being a function of a desired output format of the mixed signals. The subset of opcodes is then utilized to control the means for selectively switching among the received graphics and video signals to create the desired output format. The selective switching is accomplished on a pixel by pixel basis.

System and method for the mixing of graphics and video signals

A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Video processing apparatus, systems and methods

A method is disclosed for controlling tearing in a display control system which includes first and second buffers, with input of data to a selected one of the buffers controlled by an input pointer and output of data from a selected one of the buffers controlled by an output pointer. Data is first input into the first buffer and substantially simultaneously data is output from the first buffer. The output pointer is then toggled such that data is input into the first buffer and output from the second buffer. Next, the input pointer is toggled, such that it is input into the second buffer and data is output from the second buffer. The output pointer is again toggled such that data is output from the first buffer and input into the second buffer.

Apparatus, systems and methods for controlling tearing during the

A memory bandwidth allocation scheme in a computer system having a unified memory architecture. When a first device requesting access to a resource detects that two higher priority devices are also requesting access to the same resource, the first device shuts itself down. Accordingly, the first device deactivates its access request signals and clears its buffers. Then, the first device reactivates itself when it receives a graphics VSYNC signal. This allocation scheme ensures that the arbiter will not get stuck in a loop serving only high priority requests and not serving lower priority requests.

Growing community of inventors

Plano, TX, United States of America

Robert M Nally