Xilinx, Inc.

Robert M McGee

Ralph D Wittig

Philip Bryn James-Roxby

Brendan K Bridgford

Richard DeFelice

Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.

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Placitas, NM, United States of America

Robert M McGee