Synopsys, Inc.

Robert M Lugg

Michael Lawrence Rieger

Michel Luc Cote

Philippe Hurat

Jeff Mayhew

Sooryong Lee

Levi D Barnes

Hans-Jürgen Stock

Sunggon Jung

Xiaohai Li

Thomas Heribert Mülders

Rainer Zimmermann

Jiuzhou Tang

Dereje Shewaseged Woldeamanual

Georg Albert Viehöver

A computational lithography process uses machine learning models. An aerial image produced by a lithographic mask is first calculated using a two-dimensional model of the lithographic mask. This first aerial image is applied to a first machine learning model, which infers a second aerial image. The first machine learning model was trained using a training set that includes aerial images calculated using a more accurate three-dimensional model of lithographic masks. The two-dimensional model is faster to compute than the three-dimensional model but it is less accurate. The first machine learning model mitigates this inaccuracy.

Large scale computational lithography using machine learning models

Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural network, can then be used to predict a set of failures for a given design intent. Next, for each predicted failure, a reticle enhancement technique (RET) recipe may be selected based on the failure mode of the failure, and the selected RET recipe may be applied to an area around the location of the failure.

Applying reticle enhancement technique recipes based on failure modes predicted by an artificial neural network

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value) with a new layer, or alternatively using a conventional layer (e.g. metal) with a new datatype (e.g. value), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Silicon tolerance specification using shapes as design intent markers

One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print during a lithography process. Next, the system modifies the AF-printing hotspot by: (1) modifying the set of assist features; and (2) performing optical-proximity-correction (OPC) on the one or more target patterns. The system then performs a lithography simulation on the modified AF-printing hotspot to determine if: (1) a through-process-window associated with the modified AF-printing hotspot is acceptable; and (2) no assist feature in the modified set of assist features is expected to print. If so, the system replaces the AF-printing hotspot with the modified AF-printing hotspot.

Method and apparatus for correcting assist-feature-printing errors in a layout

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value 0) with a new layer, or alternatively using a conventional layer (e.g. metal 3) with a new datatype (e.g. value 1), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

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Hillsboro, OR, United States of America

Robert M Lugg