Sun Microsystems, Inc.

Oracle America, Inc.

Robert M Lane

Kenneth Tracton

Jan Lodewijk Bonebakker

Zenon Fortuna

Paul A Riethmuller

A Nyquist sampling frequency is determined for performance counter events to be measured. Based on the Nyquist sampling frequencies, a schedule for measuring the performance counter events is determined. The performance counter event measurements are then conducted in accordance with the schedule, whereby the measurements yield a set of sample data for each performance counter event. A signal reconstruction algorithm is applied to the set of sample data for each performance counter event to reconstruct an essentially complete signal for each performance counter event. The essentially complete signal for each performance counter event is then used to improve either a design or a utilization of either a microprocessor or an application to be executed on the microprocessor.

Methods for optimizing computer system performance counter utilization

A method for measuring system performance involves binding a sampling thread to a central processing unit (CPU), starting a soaker thread and binding the soaker thread to the CPU, assigning the soaker thread a lowest priority and scheduling class, placing the soaker thread in a scheduling mechanism based on the lowest priority and scheduling class, and suspending the soaker thread. If a hardware counter is kernel-only, then the following steps are performed: initializing the hardware counters, resuming the soaker thread, and executing the soaker thread if there is no scheduler item of equal or higher priority, where the scheduler item is within the scheduling mechanism.

Method and system to measure system performance

One embodiment of the present invention provides a system for mapping memory addresses to cache entries. The system operates by first receiving a memory request at the cache memory, wherein the memory request includes a memory address. The system then partitions the memory address into a set of word offset bits and a set of higher-order bits. Next, the system maps the memory address to a cache entry by computing a modulo operation on the higher-order bits with respect to an integer and using the result as the cache index.

Method and apparatus for mapping memory addresses to corresponding cache entries

One embodiment of the present invention provides a system that facilitates performing an efficient wildcard search on a field within a relational database table. The system operates by receiving a query with a search string that includes a wildcard and a sub-string. In order to process this query, the system identifies rows in a table in which a target column contains a string that matches search string. This is accomplished by looking up rows in the table that match the search string by looking up the sub-string in a sub-string index for the target column, wherein this sub-string index allows a given string in the target column to be rapidly identified based upon a sub-string of the given string. Next, the system accesses the matching rows in order to process the query. In one embodiment of the present invention, the wildcard is a leading wildcard that precedes the sub-string. In a variation on this embodiment, the search string additionally includes a trailing wildcard that follows the sub-string.

Method and apparatus for facilitating wildcard searches within a relational database

A method is provided for I/O data transfer between memory and disk. In one embodiment, an application program generates N data transfer requests. Thereafter, a data transfer list is created that comprises N entries each comprising a file sector descriptor and a buffer address. The application program is suspended in favor of initiating the operating system. Thereafter, N data transfers are performed, each one of which comprises transferring data between a file sector and a buffer identified by the file sector descriptor and a buffer address, respectively, contained in one of the entries of the data transfer list. On completion of N data transfers, the operating system is suspended and the application program is reinitiated.

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Dixon, CA, United States of America

Robert M Lane