International Business Machines Corporation

Robert M Hornung

Gerard M Lebesnerais

Jean-Paul J Nuez

Francois X Delaporte

Ieng Ong

Martine Bonneau

Eric Gouze

Jean-Marc Piccino

Anne-Marie Lamouroux

A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, . . . ) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

Gate array cell having FETs of different and optimized sizes

A system is disclosed for compensating for the offset voltage problem which occurs in certain types of differential amplifiers; a differential amplifier, in the form of an operational amplifier, is provided with two generators of input signals whose difference is to be amplified; further included is an offset voltage compensation loop comprising a comparator, an n-bit up/down counter and a digital analog converter means; the output of said means being connected to said generators of input signals so as to modulate the input signals; and said digital analog converter means including first and second n-1 bit digital analog converters.

System for compensating the offset voltage of a differential amplifier

Integrated Injection Logic (I.sup.2 L) Structures are disclosed. The disclosure includes integrated injection logic cell structures of the type including an injector and a plurality of adjacent NPN transistors spaced from said injector, characterized in that at least two PNP transistors have different factors L.sub.B /W.sub.B, where L.sub.B is the base dimension of the NPN transistor opposite the injector, and W.sub.B is the base width of the PNP transistor of the injector.

Semiconductor integrated injection logic structure controlled by the

A method and structure for correcting the voltage coefficient of resistance (VCR) of a resistor in a semiconductor body is described. The resistor may be diffused or ion implanted of one conductivity and formed in an isolated layer of the opposite type of conductivity. The layer is typically an epitaxial layer. A potential V.sub.1 is applied to one end of the resistor and a potential V.sub.2 being applied to the opposite end. The method provides means for controlling variations of the potential difference between the resistive region and the epitaxial layer, either to minimize them or to cause the distortions generated by such variations to be compensated for by equal distortions of opposite directions, such that the overall distortion will be equal to zero. There is provided means to cause the potential of the epitaxial layer to reach a suitable value, preferably a value that varies in the same manner as the average value of the resistor whose VCR is to be corrected.

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Evry, France

Robert M Hornung