Texas Instruments Corporation

Robert M Higgins

Xiaoju Wu

Jonathan Philip Davis

Li Wang

Henry Litzmann Edwards

Tathagata Chatterjee

Shariq Arshad

Bhaskar Srinivasan

Honglin Guo

Sudtida Lavangkul

Pushpa Mahalingam

Richard Allen Faust

Yanbiao Pan

Andrew Frank Burnett

Venugopal Balakrishna Menon

Anagha Shashishekhar Kulkarni

A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.

Contamination detection method

A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

Shallow trench isolation processing with local oxidation of silicon

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch

Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

Carbon and/or oxygen doped polysilicon resistor

The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

High reliability polysilicon components

Growing community of inventors

Plano, TX, United States of America

Robert M Higgins