Taiwan Semiconductor Manufacturing Comp. Ltd.

Robert Lo

Jui-Jen Wu

Kun-Hsi Li

Shau-Wei Lu

A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

Memory write assist

A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Growing community of inventors

Shin-Chu, Taiwan

Robert Lo